Semiconductor package and method
A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.
1 . A method, comprising:
attaching a plurality of interconnect structures to a carrier substrate, wherein each interconnect structure of the plurality of interconnect structures individually comprises:
a redistribution structure;
a first encapsulant on the redistribution structure;
an interconnect component in the first encapsulant, the interconnect component comprising electrical routing, the interconnect component being surrounded by the first encapsulant, the interconnect component and the redistribution structure being vertically separated by the first encapsulant;
a via extending through the first encapsulant to physically and electrically connect to the redistribution structure;
depositing a second encapsulant on the plurality of interconnect structures, wherein adjacent interconnect structures of the plurality of interconnect structures are laterally separated by the second encapsulant;
after depositing the second encapsulant and removing the carrier substrate;
after depositing the second encapsulant and the removing the carrier substrate, attaching a first core substrate to the redistribution structure of at least one interconnect structure of the plurality of interconnect structures, wherein the first core substrate is electrically connected directly to the redistribution structure, wherein the first core substrate is attached to a first side of the plurality of interconnect structures; and
attaching a plurality of semiconductor devices to the plurality of interconnect structures, wherein each semiconductor device of the plurality of semiconductor devices is electrically connected to the via of a respective interconnect structure of the plurality of interconnect structures, wherein the plurality of semiconductor devices are attached to a second side of the plurality of interconnect structures that is opposite the first side.
2 . The method of claim 1 , wherein each semiconductor device of the plurality of semiconductor devices is electrically connected to the interconnect component of a respective interconnect structure of the plurality of interconnect structures.
3 . The method of claim 1 , wherein the at least one interconnect structure of the plurality of interconnect structures further comprises an integrated passive device (IPD).
4 . The method of claim 1 , wherein the plurality of semiconductor devices are attached after attaching the first core substrate.
5 . The method of claim 1 , further comprising depositing an underfill between the first core substrate and the plurality of interconnect structures.
6 . The method of claim 1 , wherein the via of a first interconnect structure of the plurality of interconnect structures has a larger width than the via of a second interconnect structure of the plurality of interconnect structures.
7 . A method, comprising:
forming a first interconnect structure, comprising:
forming first vias on a first carrier;
depositing a first molding material over the first vias and the first carrier;
forming a redistribution structure on the first vias and a first side of the first molding material, wherein the redistribution structure is electrically connected to the first vias;
removing the first carrier; and
forming second vias on the first vias and a second side of the first molding material opposite the first side, wherein the second vias are electrically connected to the first vias;
after forming the second vias on the first vias, forming a connection structure, comprising:
placing the first interconnect structure and a second interconnect structure on a second carrier;
depositing a second molding material between the first interconnect structure and the second interconnect structure; and
performing a planarization process on the second molding material, the first interconnect structure, and the second interconnect structure, wherein after performing the planarization process, the second molding material and the second vias of the first interconnect structure are coplanar;
connecting a first core substrate to the connection structure, wherein the first core substrate is connected to the redistribution structure of the first interconnect structure; and
connecting a first semiconductor device to the connection structure, wherein the first semiconductor device is connected to the second vias of the first interconnect structure, wherein forming the first interconnect structure further comprises placing an integrated passive device (IPD) on the first carrier and depositing the first molding material over the IPD, wherein the second vias are formed over and electrically connected to the IPD.
8 . The method of claim 7 , wherein the second interconnect structure comprises a redistribution structure, and wherein the first core substrate is connected to the redistribution structure of the second interconnect structure.
9 . The method of claim 7 , wherein a sidewall of the first core substrate protrudes beyond a sidewall of the connection structure.
10 . The method of claim 7 , wherein connecting the first core substrate to the connection structure comprises bonding the first core substrate to the connection structure using solder bumps.
11 . A method comprising:
connecting a redistribution substrate to a plurality of interconnect structures, wherein each interconnect structure of the plurality of interconnect structures respectively comprises:
a redistribution structure;
a first encapsulant on the redistribution structure, the redistribution structure being on a first side of the first encapsulant;
a through via on the redistribution structure and extending through the first encapsulant;
an integrated device adjacent the through via, wherein the integrated device is surrounded by the first encapsulant; and
a first conductive via on the through via and a second conductive via on the integrated device, the first and second conductive vias being on a second side of the first encapsulant opposite the first side;
depositing a second encapsulant on the plurality of interconnect structures, wherein the second encapsulant separates adjacent interconnect structures of the plurality of interconnect structures, wherein the second encapsulant physically contacts the first encapsulant, wherein the redistribution substrate is free of the second encapsulant;
performing a planarization process on the second encapsulant and at least one of the plurality of interconnect structures, wherein after performing the planarization process, the second encapsulant and the first and second conductive vias of the at least one of the plurality of interconnect structures are coplanar; and
connecting a plurality of semiconductor devices to the plurality of interconnect structures, wherein at least one semiconductor device of the plurality of semiconductor devices is connected to two adjacent interconnect structures of the plurality of interconnect structures.
12 . The method of claim 11 , wherein the second encapsulant is deposited on the plurality of interconnect structures before the redistribution substrate is connected to the plurality of interconnect structures.
13 . The method of claim 11 further comprising depositing an underfill between the redistribution substrate and the plurality of interconnect structures.
14 . The method of claim 11 , wherein the redistribution substrate is connected to the redistribution structures of the plurality of interconnect structures.
15 . The method of claim 11 , wherein an integrated device of the plurality of interconnect structures is connected to at least two semiconductor devices of the plurality of semiconductor devices.
16 . The method of claim 13 , wherein the underfill physically contacts the redistribution structures of the plurality of interconnect structures.
17 . The method of claim 11 , wherein the integrated device of the plurality of interconnect structures comprises electrical routing.
18 . The method of claim 11 , further comprising:
attaching the plurality of interconnect structures to a carrier substrate; and
after depositing the second encapsulant, removing the carrier substrate.
19 . The method of claim 11 , wherein the at least one semiconductor device of the plurality of semiconductor devices extends from a first interconnect structure of the plurality of interconnect structures over the second encapsulant to a second interconnect structure of the plurality of interconnect structures.