Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
1. An accumulated charge control (ACC) transistor comprising:
a gate;
a drain;
a source;
a body, wherein the ACC transistor is configured to selectively operate in an on state or an off state, and wherein the ACC transistor is a metal-oxide-semiconductor field effect transistor;
a first accumulated charge sink (ACS) region coupled to the body at a first side of the body and configured to control, via the first ACS region, charge accumulated within the body of the ACC transistor during at least a portion of the off state to improve a linearity of the ACC transistor;
a second ACS region coupled to the body at a second side of the body opposite the first side and configured to control, via the second ACS region, the charge accumulated within the body of the ACC transistor during at least the portion of the off state to improve the linearity of the ACC transistor, wherein the charge accumulated within the body is associated with carriers having a polarity opposite a polarity of carriers in the drain and the source when the ACC transistor is operated in the on state; and
a structure coupled to the first ACS region and the second ACS region.
2. The ACC transistor of claim 1 , wherein the structure is configured to short the first ACS region and the second ACS region.
3. The ACC transistor of claim 1 , wherein the first ACS region and the second ACS region are disposed symmetric with respect to the body.
4. The ACC transistor of claim 1 , wherein the first ACS region is configured to receive, during at least the portion of the off state of the ACC transistor, a first bias voltage to control the charge accumulated within the body via the first ACS region.
5. The ACC transistor of claim 4 , wherein the first bias voltage is equal to or more negative than a bias voltage applied to the source and a bias voltage applied to the drain.
6. The ACC transistor of claim 4 , wherein the first ACS region is configured to receive the first bias voltage to control charge that, without the first bias voltage received, would accumulate in the body.
7. The ACC transistor of claim 4 , wherein the second ACS region is configured to receive, during at least the portion of the off state of the ACC transistor, a second bias voltage to control the charge accumulated within the body via the second ACS region.
8. The ACC transistor of claim 1 , wherein the structure comprises a metal layer.
9. The ACC transistor of claim 1 , wherein the structure comprises a semiconductor layer.
10. The ACC transistor of claim 1 , wherein the first ACS region is disposed at a first end of the ACC transistor, and wherein the second ACS region is disposed at a second end of the ACC transistor opposite the first end.
11. The ACC transistor of claim 1 , wherein the first ACS region and the second ACS region are further coupled to the gate, and wherein both the first ACS region and the second ACS region are configured to remove the charge accumulated within the body of the ACC transistor during at least the portion of the off state.
12. The ACC transistor of claim 1 , further comprising a diode coupled between the first ACS region and the gate.
13. The ACC transistor of claim 1 , further comprising:
a first electrical contact region coupled to the first ACS region; and
a second electrical contact region coupled to the second ACS region.
14. The ACC transistor of claim 13 , wherein the structure is configured to electrically connect the first ACS region and the second ACS region through the first electrical contact region and the second electrical contact region.
15. The ACC transistor of claim 13 , wherein the first electrical contact region and the second electrical contact region are P-type regions, and wherein the source and the drain are N-type regions.
16. The ACC transistor of claim 13 , wherein the first electrical contact region is coextensive with the first ACS region, and wherein the second electrical contact region is coextensive with the second ACS region.
17. The ACC transistor of claim 1 , wherein the ACC transistor is implemented in a semiconductor-on-insulator technology.
18. A switch comprising the ACC transistor of claim 1 , the switch further comprising:
a first port; and
a second port, wherein the ACC transistor is configured to selectively connect the first port to the second port.
19. The ACC transistor of claim 1 , wherein the drain is at a third side of the body different from the first and second sides and the source is at a fourth side of the body opposite the third side.
20. The ACC transistor of claim 1 , wherein:
the source and the drain are associated with a first conductivity type, the body is associated with a second conductivity type opposite the first conductivity type, and the first ACS region comprises material doped with a dopant associated with the first conductivity type.
21. The ACC transistor of claim 1 , wherein:
the source and the drain are associated with a first conductivity type, the body is associated with a second conductivity type opposite the first conductivity type, and the first ACS region comprises material doped with a dopant associated with the second conductivity type.
22. The ACC transistor of claim 1 , wherein the first ACS region, the second ACS region, and the structure are collectively configured to set a voltage difference between the body and the gate to zero or substantially zero.
23. The ACC transistor of claim 1 , wherein the ACC transistor is configured to operate in the off state when a bias voltage applied to the gate is negative relative to a bias voltage applied to the drain and a bias voltage applied to the source.
24. A method for controlling accumulated charge in a transistor, the method comprising:
controlling charge accumulated within a body of the transistor during at least a portion of an off state of the transistor via a first accumulated charge sink (ACS) region of the transistor coupled to the body at a first side of the body to improve a linearity of the transistor, wherein the transistor is a metal-oxide-semiconductor field effect transistor; and
controlling the charge accumulated within the body during at least the portion of the off state of the transistor via a second ACS region coupled to the body at a second side of the body opposite the first side to improve the linearity of the transistor, wherein the charge accumulated within the body is associated with carriers having a polarity opposite a polarity of carriers in a drain of the transistor and a source of the transistor when the transistor is operated in the on state, wherein the first ACS region and the second ACS region are coupled via a structure.
25. The method of claim 24 , wherein the structure shorts the first ACS region and the second ACS region.
26. The method of claim 24 , wherein the first ACS region and the second ACS region are disposed symmetric with respect to the body.
27. The method of claim 24 , wherein the controlling the charge via the first ACS region comprises receiving, by the first ACS region during at least the portion of the off state of the transistor, a first bias voltage.
28. The method of claim 27 , wherein the first bias voltage is equal to or more negative than a bias voltage applied to the source of the transistor and a bias voltage applied to the drain of the transistor.
29. The method of claim 27 , wherein the first bias voltage is received by the first ACS region to control charge that, without the first bias voltage received, would accumulate in the body.
30. The method of claim 27 , wherein the controlling the charge via the second ACS region comprises receiving, by the second ACS region during at least the portion of the off state of the ACC transistor, a second bias voltage, and wherein the second bias voltage is received by the second ACS region to control charge that, without the second bias voltage received, would accumulate in the body.
31. The method of claim 24 , wherein the structure comprises a metal layer.
32. The method of claim 24 , wherein the structure comprises a semiconductor layer.
33. The method of claim 24 , wherein the first ACS region is disposed at a first end of the transistor, and wherein the second ACS region is disposed at a second end of the transistor opposite the first end.
34. The method of claim 24 , wherein the first ACS region and the second ACS region are further coupled to a gate of the transistor.
35. The method of claim 24 , wherein the first ACS region is coupled to a first electrical contact region, wherein the second ACS region is coupled to a second electrical contact region, and wherein the structure electrically connects the first ACS region and the second ACS region through the first electrical contact region and the second electrical contact region.
36. The method of claim 35 , wherein the first electrical contact region and the second electrical contact region are P-type regions, and wherein a source of the transistor and a drain of the transistor are N-type regions.
37. The method of claim 35 , wherein the first electrical contact region is coextensive with the first ACS region, and wherein the second electrical contact region is coextensive with the second ACS region.
38. The method of claim 24 , wherein the transistor is implemented in a semiconductor-on-insulator technology.
39. The method of claim 24 , wherein the drain of the transistor is at a third side of the body different from the first and second sides and the source of the transistor is at a fourth side of the body opposite the third side.
40. The method of claim 24 , wherein:
the source and the drain of the transistor are associated with a first conductivity type,
the body is associated with a second conductivity type opposite the first conductivity type, and
the first ACS region comprises material doped with a dopant associated with the first conductivity type.
41. The method of claim 24 , wherein:
the source and the drain of the transistor are associated with a first conductivity type,
the body is associated with a second conductivity type opposite the first conductivity type, and
the first ACS region comprises material doped with a dopant associated with the second conductivity type.
42. The method of claim 40 , wherein the first conductivity type is an n-type conductivity, and wherein the second conductivity type is a p-type conductivity.
43. The method of claim 24 , further comprising setting, by the first ACS region, the second ACS region, and the structure collectively, a voltage difference between the body and a gate of the transistor to zero or substantially zero.
44. The switch of claim 18 , wherein the ACC transistor is configured to:
connect the first port to the second port when the ACC transistor is operated in the on state; and
not connect the first port to the second port when the ACC transistor is operated in the off state.