Storage system with interconnected solid state disks
An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.
1. At least one non-transitory computer readable medium, comprising a set of instructions, which when executed by a computing device connected to at least one memory device, cause the computing device to:
determine a receiver memory device to which to send one or more of data or a command;
cause transmission of one or more of data or the command to a destination memory device, the transmission to use a first path from a transmitter to the destination memory device, wherein the first path is to include the receiver memory device and the destination memory device or at least one memory device that is to forward the one or more of data or the command to another memory device; and
based on an indication of the one or more of the data or the command having not been received by at least one memory device in the first path, cause retransmission of one or more of the data or the command using a second path, wherein the second path omits a non-responsive memory device, wherein the receiver memory device comprises an integrated component memory and switch device, and wherein the at least one memory device comprises an integrated component memory and switch device.
2. The computer readable medium of claim 1 , wherein the command comprises a command to read or write data and an address.
3. The computer readable medium of claim 1 , wherein the computing device is to determine a receiver memory device to which to send one or more of data or the command based on a table and wherein the table comprises a routing table that includes one or more of: a device identification (ID), a first peer connection, or a second peer connection.
4. The computer readable medium of claim 1 , wherein the non-responsive memory device comprises a device that has been removed or does not respond in an amount of time.
5. The computer readable medium of claim 1 , wherein the indication of the one or more of the data or the command having not been received by the memory device in the first path comprises failure to receive an acknowledgement message.
6. The computer readable medium of claim 1 , wherein the destination memory device comprises byte-addressable memory.
7. An apparatus comprising:
a processor and
circuitry, coupled to the processor, and configured to:
determine a receiver memory device to which to send one or more of data or a command;
cause transmission of one or more of data or the command to a destination memory device, the transmission to use a first path from a transmitter to the destination memory device, wherein the first path is to include the receiver memory device and the destination memory device or at least one memory device that is to forward the one or more of data or command to another memory device; and
based on an indication of the one or more of the data or the command having not been received by a memory device in the first path, cause retransmission of one or more of the data or the command by a second path, wherein the second path omits a non-responsive memory device, wherein the receiver memory device comprises an integrated component memory and switch device, and wherein the at least one memory device comprises an integrated component memory and switch device.
8. The apparatus of claim 7 , wherein the command comprises a command to read or write data and an address.
9. The apparatus of claim 7 , wherein the circuitry is to determine a receiver memory device to which to send one or more of data or the command based on a table and wherein the table comprises a routing table that includes one or more of: a device identification (ID), a first peer connection, or a second peer connection.
10. The apparatus of claim 7 , wherein the non-responsive memory device comprises a device that has been removed or does not respond in an amount of time.
11. The apparatus of claim 7 , wherein the non-responsive memory device comprises a memory device and a switch device.
12. The apparatus of claim 7 , wherein the indication of the one or more of the data or the command having not been received by the memory device in the first path comprises failure to receive an acknowledgement message.
13. The apparatus of claim 7 , wherein the destination memory device comprises byte-addressable memory.
14. The apparatus of claim 7 , wherein to forward the one or more of data or the command to another memory device, the at least one memory device is to access a routing table to determine a next memory device to which to forward the one or more of data or command.
15. The apparatus of claim 7 , wherein to forward the one or more of data or command to another memory device, the at least one memory device is to access a routing table to determine a next memory device to which to forward the one or more of data or the command and wherein retransmission of one or more of the data or the command by a second path comprises the at least one memory device is to access the routing table to determine a next memory device to which to forward the one or more of data or command along the second path.
16. A method comprising:
determining a receiver memory device to which to send one or more of data or a command;
causing transmission of one or more of data or the command to a destination memory device, the transmission to use a first path from a transmitter to the destination memory device, wherein the first path is to include the receiver memory device and the destination memory device or at least one memory device that is to forward the one or more of data or the command to another memory device; and
based on an indication of the one or more of the data or command having not been received by a memory device in the first path, causing retransmission of one or more of the data or command using a second path, wherein the second path omits a non-responsive memory device, wherein the receiver memory device comprises an integrated component memory and switch device and wherein the at least one memory device comprises an integrated component memory and switch device.
17. The method of claim 16 , wherein the command comprises a command to read or write data and an address.
18. The method of claim 16 , wherein the determining a receiver memory device to which to send one or more of data or command is based on a table and wherein the table comprises a routing table that includes one or more of: a device identification (ID), a first peer connection, or a second peer connection.
19. The method of claim 16 , wherein the non-responsive memory device comprises a device that has been removed or does not respond in an amount of time.
20. The method of claim 16 , wherein the indication of the one or more of the data or the command having not been received at the memory device in the first path comprises failure to receive an acknowledgement message.
21. The method of claim 16 , wherein the destination memory device comprises byte-addressable memory.