Low-k feature formation processes and structures formed thereby
Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a gate structure over a semiconductor fin;
depositing a low-k spacer material over the gate structure, wherein the depositing the low-k spacer material comprises:
introducing a first carbon-containing precursor at a first flow rate;
after the introducing the first carbon-containing precursor at the first flow rate, introducing an oxidizing precursor at a second flow rate; and
after the introducing the oxidizing precursor at the second flow rate, introducing the first carbon-containing precursor at a third flow rate different from the first flow rate; and
etching the low-k spacer material to form a spacer, the spacer having a density of between 1.0 g/cm 3 to 3.0 g/cm 3 .
2. The method of claim 1 , wherein the low-k spacer material has a carbon concentration in a range from greater than 0 atomic percent (at. %) to 30 at. %.
3. The method of claim 1 , wherein the low-k spacer material has a nitrogen concentration less than about 3 at. %.
4. The method of claim 1 , wherein the first carbon-containing precursor does not comprise nitrogen.
5. The method of claim 1 , wherein the depositing the low-k spacer material deposits the low-k spacer material adjacent to a first spacer layer.
6. The method of claim 1 , wherein the introducing the first carbon-containing precursor at the first flow rate is performed for a first duration, the introducing the first carbon-containing precursor at the third flow rate is performed for a second duration different from the first duration.
7. The method of claim 1 , wherein the depositing the low-k spacer material further introduces a catalyst with the first carbon-containing precursor.
8. A method comprising:
forming a dummy gate electrode over a semiconductor material, the semiconductor material comprising multiple channel regions;
depositing a low-k material adjacent to the dummy gate electrode, the depositing the low-k material comprising:
pulsing a silicon-carbon precursor over the dummy gate electrode a first time;
after the pulsing the silicon-carbon precursor the first time, pulsing an oxidizing precursor over the dummy gate electrode a first time; and
after the pulsing the oxidizing precursor over the dummy gate electrode the first time, pulsing the silicon-carbon precursor over the dummy gate electrode a second time, wherein the pulsing the silicon-carbon precursor over the dummy gate electrode the second time is done for a different duration than the pulsing the silicon-carbon precursor over the dummy gate electrode the first time, wherein after the pulsing the silicon-carbon precursor the second time the low-k material has a carbon concentration in a range from greater than 0 atomic percent (at. %) to 30 at. % and a nitrogen concentration less than about 3 at. %; and
patterning the low-k material into a first spacer.
9. The method of claim 8 , wherein the depositing the low-k material deposits the low-k material in physical contact with a spacer layer.
10. The method of claim 8 , further comprising removing the dummy gate electrode after the patterning the low-k material.
11. The method of claim 8 , wherein the silicon-carbon precursor further comprises a silicon compound.
12. The method of claim 8 , wherein the pulsing the silicon-carbon precursor over the dummy gate electrode the second time is done at a different flow rate than the pulsing the pulsing the silicon-carbon precursor over the dummy gate electrode the first time.
13. The method of claim 8 , wherein the multiple channel regions are part of a semiconductor fin.
14. The method of claim 8 , further comprising pulsing pyridine over the dummy gate electrode a first time.
15. A method of manufacturing a semiconductor device, the method comprising:
forming a dummy gate electrode over a semiconductor fin over a substrate; and
forming a spacer located adjacent to the dummy gate electrode, wherein at least a portion of the spacer has a density of between about 1 g/cm 3 and 3 g/cm 3 , a non-zero carbon concentration less than about 30 at. % and a non-zero nitrogen concentration of less than about 3 at. %.
16. The method of claim 15 , wherein the forming the spacer comprises forming a spacer layer with a conformity of greater than 95% and less than 105%.
17. The method of claim 15 , further comprising replacing the dummy gate electrode after the forming the spacer.
18. The method of claim 15 , wherein the forming the spacer further comprises flowing a catalyst and a first precursor over the dummy gate electrode.
19. The method of claim 18 , wherein the catalyst is pyridine.
20. The method of claim 15 , wherein the spacer has an increasing carbon concentration from a first side of the spacer to a second side of the spacer.