Integrated circuit chip having BS-PDN structure

1. An integrated circuit chip comprising:

a substrate having an active surface and a back surface opposite to the active surface;

a front-end-of-line (FEOL) structure disposed on the active surface of the substrate;

a first back-end-of-line (BEOL) structure disposed on the FEOL structure;

an intermediate connection layer disposed under the back surface of the substrate, the intermediate connection layer comprising a charge storage, and metal posts disposed around the charge storage; and

a re-distribution structure layer disposed under the intermediate connection layer,

wherein a top surface of the charge storage, that faces towards the substrate, is a part of a top surface of the intermediate connection layer, or the top surface of the charge storage is directly connected to a connection pad within the intermediate connection layer.

2. The integrated circuit chip according to claim 1 , wherein the intermediate connection layer further comprises a molding material covering surfaces of the charge storage and the metal posts.

3. The integrated circuit chip according to claim 2 , wherein the molding material comprises an epoxy molding compound.

4. The integrated circuit chip according to claim 1 , wherein a height of the charge storage is smaller than a height of each of the metal posts.

5. The integrated circuit chip according to claim 1 , wherein:

the charge storage comprises silicon (Si); and

the metal posts comprise copper (Cu).

6. The integrated circuit chip according to claim 1 , wherein the charge storage has a charge storage capacity of 200 to 400 nF/mm 2 .

7. The integrated circuit chip according to claim 1 , wherein the metal posts have a pitch of 100 to 120 μm.

8. The integrated circuit chip according to claim 1 , wherein each of the metal posts has a height of 10 to 20 μm.

9. The integrated circuit chip according to claim 1 , wherein each of the metal posts has a cylindrical shape.

10. The integrated circuit chip according to claim 1 , wherein the metal posts in the intermediate connection layer are 6,000 or more in number.

11. The integrated circuit chip according to claim 1 , wherein the top surface of the charge storage is directly connected to the connection pad within the intermediate connection layer.

12. The integrated circuit chip according to claim 1 , further comprising:

a second BEOL structure disposed between the substrate and the intermediate connection layer,

wherein a thickness of the second BEOL structure is smaller than a thickness of the first BEOL structure.

13. The integrated circuit chip according to claim 12 , wherein:

the first BEOL structure comprises wiring layers that extend in a horizontal direction and are separated from each other in a vertical direction, and the first BEOL structure further comprises at least one contact plug that connects together neighboring ones of the wiring layers; and

the second BEOL structure comprises a single-layer wiring that extends in the horizontal direction.

14. The integrated circuit chip according to claim 1 , wherein:

the FEOL structure comprises a fin field effect transistor (FinFET); and

the FinFET comprises:

a channel region extending from the substrate in a vertical direction, and

a source region and a drain region which contact an upper portion of the channel region.

15. The integrated circuit chip according to claim 1 , wherein the substrate and the intermediate connection layer directly contact each other.

16. The integrated circuit chip according to claim 1 , further comprising:

bumps disposed between the substrate and the charge storage.

17. An integrated circuit chip comprising:

a logic chip; and

a power distribution network (PDN) disposed under the logic chip,

wherein the logic chip comprises:

a substrate having an active surface and a back surface opposite to the active surface,

a front-end-of-line (FEOL) structure disposed on the active surface of the substrate and comprising a lower insulating film comprising an oxide, the FEOL structure constituting a logic cell comprising a fin field effect transistor (FinFET), and

a first back-end-of-line (BEOL) structure disposed on the FEOL structure, and

wherein the PDN comprises:

a second BEOL structure disposed under the substrate and having a smaller thickness than the first BEOL structure,

an intermediate connection layer disposed under the second BEOL structure, the intermediate connection layer comprising a charge storage, copper (Cu) posts disposed around the charge storage, and a molding material covering side surfaces of the charge storage and the copper posts, the charge storage comprising SI,

a re-distribution structure layer disposed under the intermediate connection layer, and

solder balls disposed under the re-distribution structure layer,

wherein a top surface of the charge storage, that faces towards the second BEOL structure, is a part of a top surface of the intermediate connection layer, or the top surface of the charge storage is directly connected to a connection pad within the intermediate connection layer.

18. An integrated circuit chip comprising:

a logic chip comprising a substrate and a fin field effect transistor (FinFET) on one surface of the substrate; and

a power distribution network (PDN) disposed under the logic chip,

wherein the PDN comprises:

a back-end-of-line (BEOL) structure disposed under the substrate,

an intermediate connection layer disposed under the BEOL structure, the intermediate connection layer comprising a charge storage, copper (Cu) posts disposed around the charge storage, and a molding material covering side surfaces of the charge storage and the copper posts, the charge storage comprising Si, and

a re-distribution structure layer disposed under the intermediate connection layer, and

wherein a top surface of the charge storage, that faces towards the BEOL structure, is a part of a top surface of the intermediate connection layer, or the top surface of the charge storage is directly connected to a connection pad within the intermediate connection layer.

19. The integrated circuit chip according to claim 18 , wherein a length of one side of the charge storage is 5 to 20% of a length of one side of the molding material when viewed in a plane.

20. The integrated circuit chip according to claim 18 , wherein a height of the charge storage is equal to a height of each of the copper posts.