Method and apparatus for supplying power to VLSI silicon chips
View Patent ↗An integrated circuit module, system and method of providing power and signals is disclosed that includes a silicon chip and a package substrate having voltage connections and signal connections. The silicon chip includes a silicon substrate having a top surface, a bottom surface and circuitry formed therein, one or more front-side metal layers formed on the top surface of the silicon substrate, one or more back-side metal layers formed on the bottom surface of the silicon substrate, and one or more through silicon vias (TSVs) formed through the silicon substrate for creating a conductive pathway from the back-side of the silicon substrate to the front-side of the silicon substrate, preferably closest to the silicon substrate.
1. A method of providing power and signals to an integrated circuit, the method comprising:
providing one or more signals to one or more front-side metal signal layers formed above a top surface of a silicon substrate, wherein circuitry is formed in the top surface of the silicon substrate that has one or more transistors;
providing one or more power voltages to one or more back-side metal layers formed below a bottom surface of the silicon substrate; and
providing the one or more power voltages from the one or more back-side metal layers to one or more through silicon vias (TSVs) formed through the silicon substrate and routing the one or more power voltages from the one or more TSVs through the silicon substrate to one or more front-side metal power voltage layers formed above the top surface of the silicon substrate.
2. The method of claim 1 , further comprising supplying all the signals to the one or more front-side metal signal layers.
3. The method of claim 2 , further comprising supplying all the signals to the one or more front-side metal signal layers through C4 connections.
4. The method of claim 1 , further comprising supplying all the power voltages to the one or more back-side metal layers.
5. The method of claim 1 , further comprising supplying all the power voltages to the one or more TSVs and routing the one or more power voltages from the TSVs to one or more front-side metal power voltage layers formed above and closest to the silicon substrate.
6. The method of claim 1 , further comprising supplying all the power voltages from the back-side metal layers through the silicon substrate to the one or more front-side metal power voltage layers using the one or more TSVs.
7. The method of claim 1 , further comprising routing the one or more power voltages from voltage connections on a package substrate through wire bonds to the one or more back-side metal layers.
8. The method of claim 1 , further comprising routing all the power voltages from a package substrate to the one or more back-side metal layers.
9. The method of claim 1 , wherein all the one or more power voltages are supplied from a package substrate through wire bonds to the one or more back-side metal layers and all the one or more signals are routed from the package substrate through C4 connections to the one or more front-side metal signal layers.
10. The method of claim 1 , providing all the one or more signals to the one or more front-side metal signal layers and providing no signals to the one or more back-side metal layers.
11. The method of claim 1 , providing one or more signals to or from via structures formed through one or more front-side metal layers.
12. The method of claim 1 , providing one or more signals to or from via structures formed through one or more front-side metal layers to provide the one or more signals to and from the circuitry in the silicon substrate.
13. The method of claim 1 , further comprising forming voltage planes in one or more top-side metal layers formed above and closest to the silicon substrate.
14. The method of claim 1 , further comprising:
supplying all signals in the one or more front-side metal signal layers to one or more via structures in the one or more front-side metal layers to provide the signals through one or more voltage planes in one or more top-side metal layers formed above and closest to the silicon substrate; and
providing no signals to the one or more back-side metal layers.
15. The method of claim 1 , further comprising providing the one or more power voltages supplied to the one or more front-side metal power voltage layers, by the one or more TSVs through the silicon substrate, to the circuitry formed in the top surface of the silicon substrate.
16. The method of claim 1 , further comprising supplying at least two voltage levels comprising VDD and ground to the back-side metal layers.
17. The method of claim 1 , further comprising supplying the one or more power voltages provided to the one or more front-side metal power voltage layers to the circuitry formed in the top surface of the silicon substrate.
18. The method of claim 1 , further comprising supplying, by the one or more TSVs in the silicon substrate, the one or more power voltages provided to the one or more backside metal layers to a voltage power grid formed in a top-side metal layer formed above and closest to the silicon substrate.
19. The method of claim 18 , further comprising supplying the one or more power voltages provided to the power grid formed in the top-side metal layer closest to the silicon substrate to the circuitry formed in the top surface of the silicon substrate.