Silicon based microchannel cooling and electrical package

1. A method for fabricating a chip package comprising:

prefabricating a silicon carrier to form both liquid cooling microchannels and through silicon vias for electrical interconnections to integrated circuits;

prefabricating a silicon substrate;

forming a dielectric layer between the silicon substrate and a layer of Tungsten (W);

affixing a first array of small, highly thermally conductive metallic balls between the silicon carrier and the silicon substrate;

placing the silicon carrier in contact with the first array of metallic balls;

affixing one or more chips or chip stacks to the silicon carrier using a second array of small, highly thermally conductive metallic balls;

wherein the metallic balls in the first and second arrays range in size from 2.0 to 20 microns in diameter for very high density interconnections;

forcing a liquid coolant through the liquid cooling microchannels;

introducing a plurality of through silicon vias to provide vertical electrical interconnections; and

connecting a cap over the chips using an epoxy-based adhesive.

2. The method of claim 1 wherein the electrical interconnections comprise a metallic conductor providing both electrical and thermal conduction.

3. The method of claim 1 further comprising:

placing a second silicon carrier above the integrated circuits for cooling a top and bottom of the integrated circuits, wherein the second silicon carrier comprises pre-formed through silicon vias for interconnections and liquid cooling microchannels for cooling.

4. The method of claim 3 wherein the through silicon vias comprise an integrated function of providing electrical voltage and providing decoupling capacitance.

5. The method of claim 3 further comprising:

testing chips, wafers, chip stacks and wafer stacks by providing power and cooling during test and burn in.

6. The method of claim 3 further comprising:

preheating the wafers for contact with reduced force by flowing a controlled heated liquid through the liquid cooling microchannels during probing or contact to a test head to heat said solder connections so that contact force during contact with said test head is reduced;

followed by cooling of the chip package during test.

7. The method of claim 3 further comprising testing wafers, chips, wafer stacks and chip stacks using electrical and thermal cooling means.

8. The method of claim 7 further comprising testing wafers, chips, wafer stacks and chip stacks using optical means.

9. The method of claim 3 further comprising:

preheating the chips for contact with reduced force by flowing a controlled heated liquid through the liquid cooling microchannels during probing or contact to a test head to heat said solder connections so that contact force during contact with said test head is reduced; and

followed by cooling of the chip package during test.

10. A method for fabricating a chip package comprising:

prefabricating a silicon carrier to form both liquid cooling microchannels and through silicon vias for electrical interconnections to integrated circuits;

prefabricating a silicon substrate;

forming a dielectric layer between the silicon substrate and a Copper (Cu) conductor layer;

affixing a first array of small, highly thermally conductive metallic balls between the silicon carrier and the silicon substrate;

placing the silicon carrier in contact with the first array of metallic balls;

affixing one or more chips or chip stacks to the silicon carrier using a second array of small, highly thermally conductive metallic balls;

wherein the metallic balls in the first and second arrays range in size from 2.0 to 20 microns in diameter for very high density interconnections;

forcing a liquid coolant through the liquid cooling microchannels;

introducing a plurality of through silicon vias to provide vertical electrical interconnections; and

connecting a cap over the chips using a silicon-based adhesive.