Ferroelectric memory chiplet in a multi-dimensional packaging
A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.
1. An apparatus comprising:
a substrate;
a first die comprising a switch and a first plurality of input-output transceivers, wherein the first die is on the substrate;
a memory die on the first die via a memory interface, wherein the first die includes a memory controller to manage data traffic to the memory die;
a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers, and wherein the second die is on the memory die; and
a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os, and wherein the third die in on the second die.
2. The apparatus of claim 1 , wherein the memory interface is one of: DDR or CXL.
3. The apparatus of claim 1 , wherein the memory-side buffer includes cache with orthogonal indexing.
4. The apparatus of claim 1 , wherein the second die includes a controller for the coherent cache or memory-side buffer.
5. The apparatus of claim 1 , wherein the first die, the second die, and the third die are coupled to one another via at least one of: micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate (COWOS), or embedded multi-die interconnect bridge.
6. The apparatus of claim 1 , wherein the second die is independent of through-silicon-vias (TSV).
7. The apparatus of claim 1 , wherein the third die includes a plurality of cache banks, a local cache controller, a non-volatile controller, and a reliability logic coupled together.
8. The apparatus of claim 7 , wherein each of the plurality of cache banks includes a data bank and an associated tag, an endurance controller, a lookup logic, and/or a compute logic coupled together.
9. The apparatus of claim 1 , wherein the third die includes a memory controller to manage traffic between the second die and/or a memory die.
10. A system comprising:
a first memory comprising non-volatile memory (NVM) cells;
a second memory, wherein the first memory is coupled to the second memory;
a third memory coupled to the first memory;
a first processor coupled to the second memory; and
a second processor coupled to the third memory and the first processor, wherein the second processor comprises:
a substrate;
a first die comprising a switch and a first plurality of input-output transceivers, wherein the first die is on the substrate;
a memory die on the first die via a memory interface, wherein the first die includes a memory controller to manage data traffic to the memory die;
a second die comprising a compute logic, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers, and wherein the second die is on the memory die; and
a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, and wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os, wherein the third die in on the second die.
11. The system of claim 10 ,
wherein the second die includes a controller for the coherent cache or memory-side buffer of the third die.