IP Library Granted Patent US 11,521,928
Granted Patent B2
US 11,521,928 · App. 17/247,094 · Granted Dec 6, 2022

Reducing stress cracks in substrates

Inventors: Yong Liu (Cumberland Foreside, ME); Stephen St. Germain (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/53238H01L21/76834H01L24/29
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Quick Facts
Patent No.
US 11,521,928
App. No.
17/247,094
Granted
Dec 6, 2022
Kind
B2
Abstract

Implementations described herein are related to an improved semiconductor device package for providing an electrical connection between one or more semiconductor die and one or more substrates. The one or more substrates includes a dielectric layer having a first side and a second side opposite the first side, and a first metal layer bonded to the first side of the dielectric layer, the first metal layer having a first portion and a second portion. The semiconductor device package can also include a semiconductor die disposed onto the first metal layer within the first portion of the first metal layer. In some implementations, the one or more conducting substrates includes a direct bonded copper (DBC) substrate, i.e., the metal is copper.

Claims (39)

1. A semiconductor device package, comprising:

a direct bonded metal (DBM) substrate including:

a dielectric layer having a first side and a second side opposite the first side;

a first metal layer bonded to the first side of the dielectric layer, the first metal layer having a first portion and a second portion, the first portion of the first metal layer having a recess; and

a semiconductor die disposed on the first metal layer within the first portion of the first metal layer,

the first portion of the first metal layer having a first thickness, the second portion of the first metal layer having a second thickness with respect to the dielectric layer, the second thickness being greater than zero but less than the first thickness.

2. The semiconductor device package as in claim 1 , wherein the second portion of the first metal layer laterally surrounds at least a portion of the first portion of the first metal layer.

3. The semiconductor device package as in claim 1 , wherein the recess is located at a corner.

4. The semiconductor device package as in claim 3 ,

wherein the recess forms an edge of the first thickness at the corner.

5. The semiconductor device package as in claim 4 , wherein the corner is a first corner; and

wherein the second portion of the first metal layer protrudes beyond the first portion of the first metal layer to define a second corner of the second portion of the first metal layer.

6. The semiconductor device package as in claim 4 , wherein the recess of the first portion of the first metal layer defines a straight line connected to adjacent edges at obtuse angles.

7. The semiconductor device package as in claim 6 , wherein a distance across a surface of the second portion of the first metal layer extended beyond the corner is between about 0.3 mm and 0.7 mm.

8. The semiconductor device package as in claim 4 , wherein the recess of the first portion of the first metal layer defines a rounded edge.

9. The semiconductor device package as in claim 1 , wherein the second thickness is about half of the first thickness.

10. The semiconductor device package as in claim 1 , wherein the first portion of the first metal layer has an essentially vertical sidewall, the second portion of the first metal layer has an outer edge adjacent to a gap in the first metal layer, and wherein a distance between the essentially vertical sidewall of the first portion and the outer edge of the second portion along a surface of the second portion is between about 0.3 mm and 0.7 mm.

11. The semiconductor device package as in claim 1 , further comprising a second metal layer bonded to the second side of the dielectric layer.

12. A method, comprising:

receiving a direct bonded metal (DBM) substrate, the DBM substrate including:

a dielectric layer having a first side and a second side opposite the first side; and

a first metal layer bonded to the first side of the dielectric layer;

performing a first recess operation on a first portion of the first metal layer to produce a first recessed portion of the first portion of the first metal layer, the first recessed portion having a first thickness; and

performing a second recess operation on the first recessed portion of the first portion of the first metal layer to produce a second recessed portion of the first portion of the first metal layer, the second recessed portion having a second thickness, the second thickness being less than the first thickness.

13. The method as in claim 12 , further comprising, prior to performing the first recess operation:

performing a lithographic pattern transfer operation to define the first recessed portion and the second recessed portion of the first portion of the first metal layer.

14. The method as in claim 12 , wherein the first recessed portion of the first portion of the first metal layer has a recess at a corner.

15. The method as in claim 14 ,

wherein the recess forms an edge of the first thickness at the corner.

16. The method as in claim 15 , wherein the second recessed portion of the first portion of the first metal layer protrudes beyond the first recessed portion of the first portion of the first metal layer only outside of the corner defined by the recess of the first recessed portion of the first portion of the first metal layer.

17. The method as in claim 15 , wherein the recess of the first recessed portion of the first portion of the first metal layer defines a straight line connected to adjacent edges at obtuse angles.

18. The method as in claim 17 , wherein a distance across a surface of the second recessed portion of the first portion of the first metal layer extended beyond the corner is between about 0.3 mm and 0.7 mm.

19. The method as in claim 15 , wherein the recess of the first recessed portion of the first portion of the first metal layer defines a rounded edge.

20. A method, comprising:

receiving a direct bonded metal (DBM) substrate, the DBM substrate including:

a dielectric layer having a first side and a second side opposite the first side; and

a first metal layer bonded to the first side of the dielectric layer;

performing a recess operation on a first portion of the first metal layer to produce a first recessed portion of the first portion of the first metal layer, the first recessed portion having a first thickness; and

performing a plating operation on the first recessed portion of the first portion of the first metal layer to produce a second recessed portion of the first portion of the first metal layer, the second recessed portion having a second thickness, the second thickness being less than the first thickness.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →
SECURITY INTEREST Recorded Feb 17, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 055315/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2020
From: LIU, YONG; ST. GERMAIN, STEPHEN
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 054492/0882 →
Continuity (1)
Related Publication 20220173049A1 · Jun 2, 2022