Metal-insulator-metal capacitive structure and methods of fabricating thereof
A metal-insulator-metal (MIM) capacitor structure includes a bottom electrode, a first oxide layer adjacent the bottom electrode, and a first high-k dielectric layer over the bottom electrode and the first oxide layer. A middle electrode is over the first high-k dielectric layer and a second oxide layer is adjacent the middle electrode. A second high-k dielectric layer may be over the middle electrode and the second oxide layer, a top electrode may be over the second high-k dielectric layer.
1. A metal-insulator-metal (MIM) capacitor structure, comprising:
a bottom electrode formed over a substrate;
a first oxide layer coplanar with the bottom electrode, wherein the first oxide layer has a first thickness and the bottom electrode has a second thickness, the first thickness greater than the second thickness;
a first high-k dielectric layer on the first oxide layer and the bottom electrode;
a middle electrode over the first high-k dielectric layer;
a second oxide layer coplanar with the middle electrode;
a second high-k dielectric layer over the second oxide layer and the middle electrode; and
a top electrode over the second high-k dielectric layer.
2. The MIM capacitor structure of claim 1 , wherein the first oxide layer has a top surface substantially coplanar with a top surface of the bottom electrode.
3. The MIM capacitor structure of claim 2 , wherein the first high-k dielectric layer is disposed directly on the top surface of the first oxide layer and the top surface of the bottom electrode.
4. The MIM capacitor structure of claim 1 , further comprising a top metal layer of a multi-layer interconnect under the bottom electrode.
5. The MIM capacitor structure of claim 1 , wherein the first oxide layer is silicon oxide and the second oxide layer is silicon oxide.
6. The MIM capacitor structure of claim 1 , wherein a top surface of the first oxide layer is coplanar with a top surface of the bottom electrode.
7. The MIM capacitor structure of claim 1 , wherein the first oxide layer has a different composition that the first high-k dielectric layer.
8. The MIM capacitor structure of claim 1 , wherein a bottommost surface of the first oxide layer is lower than a bottommost surface of the bottom electrode.
9. A semiconductor device, comprising:
a metal-insulator-metal (MIM) capacitor disposed over a substrate, wherein the MIM capacitor includes:
a first electrode;
an oxide material layer adjacent the first electrode, wherein the oxide material layer has a second thickness and the first electrode has a first thickness, the second thickness greater than the first thickness;
a high-k dielectric material having a different composition than the oxide material layer on a top surface of the first electrode and a top surface of the oxide material layer; and
a second electrode over the high-k dielectric material.
10. The semiconductor device of claim 9 , wherein the top surface of the first electrode and the top surface of the oxide material layer are substantially coplanar.
11. The semiconductor device of claim 9 , further comprising:
a first conductive via extending through the high-k dielectric material and the first electrode.
12. The semiconductor device of claim 11 , further comprising:
a second conductive via extending through the high-k dielectric material and the oxide material layer.
13. The semiconductor device of claim 12 , further comprising:
a middle electrode over the high-k dielectric material wherein the second conductive via extends through the middle electrode.
14. The semiconductor device of claim 9 , wherein the oxide material layer is silicon oxide.
15. A metal-insulator-metal (MIM) capacitor structure, comprising:
a first silicon oxide layer adjacent and coplanar a bottom electrode formed over a substrate, wherein a bottom surface of the first silicon oxide layer is closer to the substrate than a bottom surface of the bottom electrode;
a first high-k dielectric layer over the first silicon oxide layer and over the bottom electrode;
a middle electrode over the first high-k dielectric layer;
a second oxide layer adjacent to the middle electrode;
a second high-k dielectric layer over the second oxide layer and over the middle electrode; and
a top electrode over the second high-k dielectric layer.
16. The MIM capacitor structure of claim 15 , wherein the first silicon oxide layer has a top surface substantially coplanar with a top surface of the bottom electrode.
17. The MIM capacitor structure of claim 15 , wherein the first high-k dielectric layer is disposed directly on the first silicon oxide layer and directly on the bottom electrode.
18. The MIM capacitor structure of claim 15 , wherein a sidewall of the first silicon oxide layer abuts a sidewall of the bottom electrode.
19. The MIM capacitor structure of claim 15 , wherein a thickness of the first silicon oxide layer is greater than a thickness of the bottom electrode.
20. The MIM capacitor structure of claim 15 , further comprising: a first conductive via extending through the bottom electrode and the top electrode and a second conductive via extending through the middle electrode.