IP Library › Granted Patent US 11,508,904
Granted Patent B2
US 11,508,904 · App. 17/308,057 · Granted Nov 22, 2022

Semiconductor device and method for fabricating the same

Inventors: Hui-Lin Wang (Taipei, TW); Chen-Yi Weng (New Taipei, TW); Yi-Wei Tseng (New Taipei, TW); Chin-Yang Hsieh (Tainan, TW); Jing-Yin Jhang (Tainan, TW); Yi-Hui Lee (Taipei, TW); Ying-Cheng Liu (Tainan, TW); Yi-An Shih (Changhua County, TW); I-Ming Tseng (Kaohsiung, TW); Yu-Ping Wang (Hsinchu, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L43/02G11C5/06G11C11/16G11C11/161H01L29/82H01L43/08H01L43/12G11C2211/5615H01L27/222
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Quick Facts
Patent No.
US 11,508,904
App. No.
17/308,057
Granted
Nov 22, 2022
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.

Claims (20)

1. A method for fabricating semiconductor device, comprising:

forming a first magnetic tunneling junction (MTJ) on a substrate;

forming a first liner on the MTJ;

forming a second liner on the first liner;

forming a first inter-metal dielectric (IMD) layer on the MTJ; and

forming a second metal interconnection on the MTJ, wherein the second liner contacts a sidewall of the second metal interconnection directly.

2. The method of claim 1 , further comprising:

forming a second IMD layer on the substrate;

forming a first metal interconnection in the second IMD layer;

forming the MTJ on the first metal interconnection; and

forming the first liner on the MTJ and the second IMD layer.

3. The method of claim 2 , wherein the first liner on a sidewall of the MTJ and the first liner on a top surface of the first IMD layer comprise different thicknesses.

4. The method of claim 3 , wherein a thickness of the first liner on the sidewall of the MTJ is less than the thickness of the first liner on the top surface of the first IMD layer.

5. The method of claim 1 , further comprising:

forming a third IMD layer on the first IMD layer; and

forming the second metal interconnection in the third IMD layer, the second liner, and the first liner to electrically connect the MTJ.

6. The method of claim 1 , further comprising removing part of the first liner to form a spacer around the MTJ before forming the second liner.

7. The method of claim 1 , further comprising performing an atomic layer deposition (ALD) process to form the second liner.

8. The method of claim 1 , wherein the first liner and the second liner comprise different materials.

9. The method of claim 8 , wherein the first liner comprises silicon nitride and the second liner comprises an oxide layer.

Priority Claims (1)
CN 201910418706.2 · May 20, 2019 · national
Continuity (2)
Division 16438480 · Jun 12, 2019
Related Publication 20210257542A1 · Aug 19, 2021
Cited By (1)
US 12,402,540