Field effect transistor structures
Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.
1 . A method of forming a semiconductor device, comprising:
providing sacrificial layers and channel layers over a substrate, wherein the sacrificial layers alternate with the channel layers;
etching through the sacrificial layers and the channel layers to form a fin;
forming a first dummy gate over the fin;
forming an adjacent second dummy gate over the fin while leaving an exposed region of the fin between the first dummy gate and the second dummy gate;
etching through the sacrificial layers and the channel layers of the fin using the dummy gates as a mask to define an opening in the exposed region of the fin, wherein:
the opening comprises a first sidewall and a second sidewall opposing the first sidewall; and
the first and second sidewalls each comprise a plurality of exposed side surfaces of the channel layers and a plurality of exposed side surfaces of the sacrificial layers; and
epitaxially growing source/drain material on the plurality of exposed side surfaces of the channel layers, wherein:
the source/drain material grown on exposed side surfaces of first vertically adjacent channel layers comprised in the first sidewall merges to form a first source/drain region;
the source/drain material grown on exposed side surfaces of second vertically adjacent channel layers comprised in the second sidewall merges to form a second source/drain region; and
the first source/drain region does not merge with the second source/drain region.
2 . The method of claim 1 , wherein providing the sacrificial layers and the channel layers over the substrate comprises depositing alternating layers of sacrificial material and channel material on an insulating layer on the substrate.
3 . The method of claim 2 , wherein the etching through the sacrificial layers and the channel layers of the fin using the dummy gates as a mask comprises etching down to the insulating layer.
4 . The method of claim 1 , wherein the fin is a nanosheet fin.
5 . The method of claim 1 , wherein the fin is a nanowire fin.
6 . The method of claim 1 , wherein an uppermost layer of the sacrificial layers and the channel layers is a sacrificial layer.
7 . The method of claim 6 , further comprising:
subsequent to the etching through the sacrificial layers and the channel layers of the fin using the dummy gates as a mask, laterally etching the exposed side surfaces of the sacrificial layers to form recessed sacrificial layers.
8 . The method of claim 7 , further comprising:
forming spacers on exposed side surfaces of the recessed sacrificial layers.
9 . The method of claim 1 , further comprising:
filling a portion of the opening between the first source/drain region and the second source/drain region with a dielectric.
10 . The method of claim 9 , further comprising:
removing the dummy gates;
removing the sacrificial layers;
forming a gate dielectric on the channel layers; and
forming a work function metal on the gate dielectric.
11 . The method of claim 1 , further comprising:
subsequent to the etching through the sacrificial layers and the channel layers of the fin using the dummy gates as a mask, laterally etching the sacrificial layers to form recessed sacrificial layers.
12 . The method of claim 11 , further comprising:
forming spacers on exposed side surfaces of the recessed sacrificial layers.
13 . The method of claim 1 , wherein epitaxially growing the source/drain material on the plurality of exposed side surfaces of the channel layers comprises growing source/drain material that follows a crystal structure of the plurality of exposed side surfaces of the channel layers.
14 . The method of claim 13 , wherein first source/drain region and the second source/drain region each comprise a bottom surface disposed on an insulating layer.
15 . A method of forming a semiconductor device, the method comprising:
providing sacrificial layers and channel layers over a substrate, wherein the sacrificial layers alternate with the channel layers, wherein a lowermost layer of the sacrificial layers and the channel layers is a sacrificial layer, and wherein an uppermost layer of the sacrificial layers and the channel layers is a sacrificial layer;
etching through the sacrificial layers and the channel layers to form a fin;
forming a first dummy gate over the fin;
forming an adjacent second dummy gate over the fin while leaving an exposed region of the fin between the first dummy gate and the second dummy gate;
etching through the sacrificial layers and the channel layers of the fin using the dummy gates as a mask to define an opening in the exposed region of the fin, wherein:
the opening comprises a first sidewall and a second sidewall opposing the first sidewall; and
the first and second sidewalls each comprise a plurality of exposed side surfaces of the channel layers and a plurality of exposed side surfaces of the sacrificial layers;
epitaxially growing source/drain material on the plurality of exposed side surfaces of the channel layers, wherein:
the source/drain material grown on exposed side surfaces of first vertically adjacent channel layers comprised in the first sidewall merges to form a first source/drain region; and
the source/drain material grown on exposed side surfaces of second vertically adjacent channel layers comprised in the second sidewall merges to form a second source/drain region; and
filling a portion of the opening between the first source/drain region and the second source/drain region with a dielectric.
16 . The method of claim 15 , wherein providing the sacrificial layers and the channel layers over the substrate comprises depositing alternating layers of sacrificial material and channel material on an insulating layer on the substrate.
17 . The method of claim 15 , wherein the fin is a nanosheet fin.
18 . The method of claim 15 , wherein the fin is a nanowire fin.
19 . The method of claim 15 , further comprising:
removing the dummy gates;
removing the sacrificial layers;
forming a gate dielectric on the channel layers; and
forming a work function metal on the gate dielectric.
20 . The method of claim 15 , wherein epitaxially growing the source/drain material on the plurality of exposed side surfaces of the channel layers comprises growing source/drain material that follows a crystal structure of the plurality of exposed side surfaces of the channel layers.
21 . The method of claim 20 , wherein the first source/drain region and the second source/drain region each comprise a bottom surface disposed on an insulating layer.