Multilevel semiconductor device and structure with image sensors
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors and alignment marks; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the third level is aligned to the alignment marks, where the second level is bonded to the first level, and where the bonded includes an oxide to oxide bond.
1. An integrated device, the device comprising:
a first level comprising a first mono-crystal layer, said first mono-crystal layer comprising a plurality of single crystal transistors;
an overlaying oxide on top of said first level;
a second level comprising a second mono-crystal layer, said second level overlaying said oxide,
wherein said second mono-crystal layer comprises a plurality of first image sensors and alignment marks; and
a third level overlaying said second level,
wherein said third level comprises a plurality of second image sensors,
wherein said third level is aligned to said alignment marks,
wherein said second level is bonded to said first level, and
wherein said bonded comprises an oxide to oxide bond.
2. The integrated device according to claim 1 ,
wherein said second mono-crystal layer is less than 5 microns thick.
3. The integrated device according to claim 1 ,
wherein said first level comprises a plurality of landing pads.
4. The integrated device according to claim 1 ,
wherein a portion of said plurality of single crystal transistors form a plurality of pixel control circuits.
5. The integrated device according to claim 1 ,
wherein at least one of said plurality of first image sensors is directly connected to at least one of said plurality of single crystal transistors.
6. The integrated device according to claim 1 ,
wherein said first image sensor is sensitive to a first set of light wavelengths and said second image sensor is sensitive to a second set of light wavelengths, and
wherein said first set of light wavelengths is different than said second set of light wavelengths.
7. The integrated device according to claim 1 ,
wherein said second level comprises an array of image sensor pixels,
wherein said first level comprises a plurality of pixel control circuits, and
wherein each of said image sensors pixels is directly connected to said pixel control circuits.
8. An integrated device, the device comprising:
a first level comprising a first mono-crystal layer, said first level comprising a plurality of single crystal transistors and alignment marks;
an overlaying oxide on top of said first level;
a second level comprising a second mono-crystal layer, said second level overlaying said oxide,
wherein said second mono-crystal layer comprises a plurality of first image sensors; and
a third level overlaying said second level,
wherein said third level comprises a plurality of second image sensors, and
wherein said second level is bonded to said first level.
9. The integrated device according to claim 8 ,
wherein said second mono-crystal layer is less than 5 microns thick.
10. The integrated device according to claim 8 ,
wherein said first level comprises a plurality of landing pads.
11. The integrated device according to claim 8 ,
wherein a portion of said plurality of single crystal transistors form a plurality of pixel control circuits.
12. The integrated device according to claim 8 ,
wherein said bonded comprises oxide to oxide bonds.
13. The integrated device according to claim 8 ,
wherein said first image sensor is sensitive to a first set of light wavelengths,
wherein said second image sensor is sensitive to a second set of light wavelengths, and
wherein said set of first light wavelengths is different than said set of second light wavelengths.
14. The integrated device according to claim 8 ,
wherein said second level comprises an array of image sensor pixels,
wherein said first level comprises a plurality of pixel control circuits, and
wherein each of said image sensor pixels is directly connected to said plurality of pixel control circuits.
15. An integrated device, the device comprising:
a first level comprising a first mono-crystal layer,
wherein said first mono-crystal layer comprises a plurality of first image sensors; and
a second level overlaying said first level,
wherein said second level comprises a plurality of second image sensors,
wherein said first image sensor comprises a first material and is sensitive to a first set of light wavelengths,
wherein said second image sensor comprises a second material and is sensitive to a second set of light wavelengths,
wherein said first material is different than said second material, and
wherein said first set of light wavelengths is different than said second set of light wavelengths.
16. The integrated device according to claim 15 , further comprising:
a third level comprising a second mono-crystal layer, said second mono-crystal layer comprising a plurality of single crystal transistors and alignment marks; and
an overlaying oxide disposed on top of said third level,
wherein said first level is aligned to said alignment marks, and
wherein said aligned comprises a less than 1 micron alignment error.
17. The integrated device according to claim 15 ,
wherein said first level comprises a plurality of landing pads.
18. The integrated device according to claim 15 , further comprising:
a third level comprising a second mono-crystal layer, said second mono-crystal layer comprising a plurality of single crystal transistors,
wherein said third level is underlaying said first level, and
wherein said single crystal transistors form a plurality of pixel control circuits.
19. The integrated device according to claim 15 , further comprising:
a third level comprising a second mono-crystal layer, said second mono-crystal layer comprising a plurality of single crystal transistors,
wherein said third level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonds.
20. The integrated device according to claim 15 ,
wherein said first material comprise a different molecule than said second material, and
wherein said first material comprise a majority of said different molecule.