Semiconductor memory device and method for manufacturing same
A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
1. A semiconductor memory device, comprising:
a semiconductor substrate;
a transistor provided on the semiconductor substrate;
a first interconnection layer provided above the transistor, the first interconnection layer including a first interconnection and a second interconnection, the first interconnection being electrically connected to the semiconductor substrate, the second interconnection being electrically connected to the transistor;
a first conductive layer provided above the first interconnection layer;
a stacked body provided above the first conductive layer and including a plurality of electrode layers stacked in a first direction;
a semiconductor member extending through the stacked body in the first direction and connected to the first conductive layer;
a charge storage member provided between the plurality of electrode layers and the semiconductor member;
a first via provided between the first conductive layer and the first interconnection and connected to the first conductive layer and the first interconnection; and
a second via extending though the stacked body and the first conductive layer and connected to the second interconnection.
2. The device according to claim 1 , further comprising:
a third interconnection provided above the stacked body and electrically connected to the second via.
3. The device according to claim 1 , wherein
the second via extends in the first direction.
4. The device according to claim 1 , wherein
the first conductive layer includes
a first portion connected to the semiconductor member, and
a second portion connected to the first via and insulated from the first portion.
5. The device according to claim 4 , wherein
the second portion is provided at a periphery of the first portion.
6. The device according to claim 4 , further comprising:
a first insulating layer provided at a periphery of the stacked body; and
an insulating plate provided inside the first insulating layer and between the first portion and the second portion.
7. The device according to claim 4 , further comprising:
a second insulating layer provided between the semiconductor substrate and the first conductive layer,
the first interconnection and the second interconnection being disposed in the second insulating layer.
8. The device according to claim 1 , further comprising:
a second conductive layer provided between the first conductive layer and the stacked body;
an intermediate insulating layer provided between the first conductive layer and the second conductive layer; and
a third via coupled between the first conductive layer and the second conductive layer.
9. The device according to claim 8 , wherein
the second conductive layer includes a first portion surrounding the semiconductor member, and
a second portion connected to the third via and insulated from the first portion.
10. The device according to claim 9 , wherein
the second portion is provided at a periphery of the first portion.
11. The device according to claim 9 , further comprising:
a first insulating layer provided at a periphery of the stacked body; and
an insulating plate provided inside the first insulating layer and between the first portion and the second portion.
12. The device according to claim 1 , wherein
the semiconductor substrate includes:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer formed in a portion of an upper layer portion of the first semiconductor layer, the second semiconductor layer being of a second conductivity type; and
a third semiconductor layer formed in a portion of an upper layer portion of the second semiconductor layer, the third semiconductor layer being of the first conductivity type, and
the first interconnection is connected to the third semiconductor layer.
13. The device according to claim 12 , wherein
the semiconductor substrate is of the second conductivity type, and
the first semiconductor layer is formed in a portion of the upper layer portion of the semiconductor substrate.