Semiconductor memory device including an asymmetrical memory core region
According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated above a substrate and extend in a first direction and a second direction, and a memory pillar that has one end connected to the substrate, has longitudinally a third direction intersecting with the first direction and the second direction, and is opposed to the plurality of control gate electrodes. The memory pillar includes a core insulating layer and a semiconductor layer arranged around the core insulating layer. The semiconductor layer includes a first portion and a second portion positioned at a substrate side of the first portion. A width in the first direction or the second direction of the semiconductor layer at at least a part of the first portion is larger than a width in the first direction or the second direction of the second portion.
1 . A semiconductor memory device comprising:
a plurality of control gate electrodes laminated above a substrate and extending in a first direction and a second direction;
a memory string including a plurality of memory cells and a plurality of select gate transistors connected in series, the plurality of memory cells and the plurality of select gate transistors being coupled to the plurality of control gate electrodes; and
a memory pillar extending in a third direction intersecting with the first direction and the second direction, and being opposed to the plurality of control gate electrodes, the memory pillar including a core insulating layer, a semiconductor layer arranged around the core insulating layer, and a memory layer including a charge accumulation layer arranged around the semiconductor layer,
wherein the semiconductor layer includes;
a first portion positioned between positions of one and the other surfaces of the plurality of control gate electrodes corresponding to the plurality of select gate transistors in the third direction, and
a second portion positioned between positions of one and the other surfaces of one of the plurality of control gate electrodes corresponding to one of the plurality of memory cells in the third direction, and a width in the first direction or the second direction of the semiconductor layer at a part of the first portion is larger than a width in the first direction or the second direction of a part of the second portion.
2 . The semiconductor memory device according to claim 1 , wherein
the core insulating layer includes:
a third portion positioned between the positions of the one and the other surfaces of the one of the plurality of control gate electrodes corresponding to the one of the plurality of select gate transistors in the third direction, and
a fourth portion positioned between the positions of the one and the other surfaces of the one of the plurality of control gate electrodes corresponding to the one of the plurality of memory cells in the third direction, and
a width in the first or the second direction of the third portion is smaller than a width in the first or the second direction of the fourth portion.
3 . The semiconductor memory device according to claim 1 , wherein
a border between the first portion and the second portion is positioned above the plurality of memory cells.
4 . The semiconductor memory device according to claim 1 , wherein
the first portion includes a third part corresponding to the select gate transistor and a fourth part corresponding to a dummy cell, and
a width in the first or the second direction of the third part is smaller than a width in the first or the second direction of the fourth part.
5 . The semiconductor memory device according to claim 4 , wherein
the core insulating layer, at a part corresponding to the third part of the memory pillar, has a larger width in the first or the second direction than a width in the first or the second direction at a part corresponding to the fourth part.
6 . The semiconductor memory device according to claim 4 , wherein
the core insulating layer is disposed only at a part corresponding to the third part of the memory pillar, and is missing at a part corresponding to the fourth part.
7 . The semiconductor memory device according to claim 1 , wherein
the core insulating layer is disposed only at the second portion, and is missing at the first portion.
8 . The semiconductor memory device according to claim 1 , wherein
the first portion is a channel region of the one of the plurality of select gate transistors,
the second portion is a channel region of the one of the plurality of memory cells, and
a width in a fourth direction perpendicular to the third direction of the semiconductor layer at the first portion is larger than a width in the fourth direction of the second portion.