Low power chip-to-chip bidirectional communications
Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.
1. A method comprising:
obtaining a set of forward-channel bits at a transmitter;
generating a plurality of symbols of a codeword based on a set of weights determined from the obtained set of forward-channel bits, the plurality of symbols of the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a corresponding weight of the set of weights applied to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors;
transmitting each symbol of the codeword as a signal over a respective wire of a multi-wire bus to a receiver; and
generating, at an output of a serializer in the transmitter, a set of bits of a secondary data link, and generating a sequence of common-mode sub-channel constituent codewords formed using a common-mode sub-channel vector that is mutually orthogonal to the plurality of sub-channel vectors, the sequence of common-mode sub-channel constituent codewords modulating a baseline voltage of the multi-wire bus according to the set of bits of the secondary data link.
2. The method of claim 1 , further comprising detecting a set of reverse-channel bits in a time interval during which the bits of the secondary data link are not being transmitted using a common-mode multi-input comparator (MIC) connected to the multi-wire bus.
3. The method of claim 2 , wherein the common-mode MIC is connected to the multi-wire bus via a set of termination impedance elements.
4. The method of claim 2 , further comprising generating a multi-bit command from the set of reverse-channel bits using a de-serializer.
5. The method of claim 1 , wherein the secondary data link comprises error information.
6. The method of claim 1 , wherein the secondary data link comprises channel equalization information.
7. The method of claim 1 , wherein the secondary data link comprises wire-specific signal skew information.
8. The method of claim 1 , wherein the common-mode sub-channel constituent codewords are transmitted at a rate slower than the set of forward-channel bits.
9. The method of claim 1 , wherein a peak-to-peak signal swing of the multi-wire bus is within a linear operating region of transistors in a receiver.
10. The method of claim 9 , wherein the symbols of the codeword have a peak-to-peak swing of 300 mV superimposed on a baseline voltage having a peak-to-peak swing of 425 mV to 475 mV.
11. An apparatus comprising:
an encoder configured to generate a plurality of symbols of a codeword based on a set of weights determined from the obtained set of forward-channel bits, the plurality of symbols of the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a corresponding weight of the set of weights applied to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors;
a plurality of line drivers configured to transmit each symbol of the codeword as a signal over a respective wire of a multi-wire bus to a receiver; and
a serializer configured to output a set of bits of a secondary data link to the plurality of line drivers, wherein the plurality of line drivers are further configured to transmit a sequence of common-mode sub-channel constituent codewords using a common-mode sub-channel vector that is mutually orthogonal to the plurality of sub-channel vectors, the plurality of line drivers configured to transmit the sequence of common-mode sub-channel constituent codewords by modulating a baseline voltage of the multi-wire bus according to the set of bits of the secondary data link.
12. The apparatus of claim 11 , further comprising a common-mode multi-input comparator (MIC) connected to the multi-wire bus, the common-mode MIC configured to detect a set of reverse-channel bits in a time interval during which the bits of the secondary data link are not being transmitted.
13. The apparatus of claim 12 , wherein the common-mode MIC is connected to the multi-wire bus via a set of termination impedance elements.
14. The apparatus of claim 12 , further comprising a de-serializer configured to receive the set of reverse-channel bits and output a multi-bit command.
15. The apparatus of claim 11 , wherein the secondary data link comprises error information.
16. The apparatus of claim 11 , wherein the secondary data link comprises channel equalization information.
17. The apparatus of claim 11 , wherein the secondary data link comprises wire-specific signal skew information.
18. The apparatus of claim 11 , wherein the common-mode sub-channel constituent codewords are transmitted at a rate slower than the set of forward-channel bits.
19. The apparatus of claim 11 , wherein a peak-to-peak signal swing of the multi-wire bus is within a linear operating region of transistors in a receiver.
20. The apparatus of claim 19 , wherein the symbols of the codeword have a peak-to-peak swing of 300 mV superimposed on a baseline voltage having a peak-to-peak swing of 425 mV to 475 mV.