Systems and methods for counting program-erase cycles of a cell block in a memory system
This disclosure proposes a method to save P/E cycling information inside NAND by using 2-byte column in programmable selective devices (e.g., SGD). The proposed method is a one-way programming method, and does not perform an erase operation within the 2-byte column. The proposed methods described herein can reduce the burden of relying upon controller SRAM/DRAM. Additionally, by storing the P/E cycling information in NAND, the P/E cycling is not lost due to a power loss event. At least one application advantageous for using NAND to store P/E cycling information includes wear leveling.
1. A method for managing a program-erase cycle count of a memory block in a memory system, the method comprising:
by a controller:
obtaining a number within a quantity of values in each of a plurality of ranges of the program-erase cycle count;
comparing the obtained number with a predetermined number representing the quantity of values in each of the plurality of ranges of the program-erase cycle count; and
when the obtained number is equal to the predetermined number, updating a bit of a plurality of program-erase cycling bits.
2. The method of claim 1 , wherein updating the bit comprises updating a drain select gate (SGD) bit.
3. The method according to claim 1 , wherein:
the bit establishes a first cycling bit of the plurality of program-erase cycling bits, the first cycling bit representing a first range of program-erase cycle count for the memory block,
the plurality of program-erase cycling bits comprises a second cycling bit that represents a second range of program-erase cycle count for the memory block, and
the first range does not overlap with the second range.
4. The method according to claim 3 , wherein updating the plurality of program-erase cycling bits comprises increasing the program-erase cycle count from the first range to the second range.
5. The method according to claim 1 , wherein updating the bit comprises updating a rightmost non-zero bit of the plurality of program-erase cycling bits from “1” to “0”.
6. The method according to claim 1 , further comprising storing the plurality of program-erase cycling bits at a location other than user data cell blocks of the memory system.
7. The method according to claim 1 , further comprising, subsequent to updating the bit, erasing data from the memory block.
8. A memory system for managing a program-erase cycle count of a memory block in a memory system, the memory system comprising:
a controller configured to:
obtain a number within a quantity of values in each of a plurality of ranges of the program-erase cycle count;
compare the obtained number with a predetermined number representing the quantity of values in each of the plurality of ranges of the program-erase cycle count; and
when the obtained number is equal to the predetermined number, update a bit of a plurality of program-erase cycling bits.
9. The memory system of claim 8 , wherein updating the bit comprises updating a drain select gate (SGD) bit.
10. The memory system according to claim 8 , wherein:
the bit establishes a first cycling bit of the plurality of program-erase cycling bits, the first cycling bit representing a first range of program-erase cycle count for the memory block,
the plurality of program-erase cycling bits comprises a second cycling bit that represents a second range of program-erase cycle count for the memory block, and
the first range does not overlap with the second range.
11. The memory system according to claim 10 , wherein the update to plurality of program-erase cycling bits comprises an increase to the program-erase cycle count from the first range to the second range.
12. The memory system according to claim 8 , wherein the update to the bit comprises an update to a rightmost non-zero bit of the plurality of program-erase cycling bits from “1” to “0”.
13. The memory system according to claim 8 , wherein the controller is further configured to store the plurality of program-erase cycling bits at a location other than user data cell blocks of the memory system.
14. The memory system according to claim 8 , further comprising, subsequent to updating the bit, erasing data from the memory block.
15. A non-volatile memory system, comprising:
a controller configured to:
obtain a number within a quantity of values in each of a plurality of ranges of a program-erase cycle count of a memory block in the memory system;
compare the obtained number with a predetermined number representing the quantity of values in each of the plurality of ranges of the program-erase cycle count; and
when the obtained number is equal to the predetermined number, update a bit of a plurality of program-erase cycling bits.
16. The non-volatile memory system of claim 15 , wherein updating the bit comprises updating a drain select gate (SGD) bit.
17. The non-volatile memory system according to claim 15 , wherein:
the bit establishes a first cycling bit of the plurality of program-erase cycling bits, the first cycling bit representing a first range of program-erase cycle count for a memory block,
the plurality of program-erase cycling bits comprises a second cycling bit that represents a second range of program-erase cycle count for the memory block, and
the first range does not overlap with the second range.
18. The non-volatile memory system according to claim 17 , wherein the update to plurality of program-erase cycling bits comprises an increase to the program-erase cycle count from the first range to the second range.
19. The non-volatile memory system according to claim 18 , wherein the update to the bit comprises an update to a rightmost non-zero bit of the plurality of program-erase cycling bits from “1” to “0”.
20. The non-volatile memory system according to claim 15 , wherein the controller is further configured to store the plurality of program-erase cycling bits at a location other than user data cell blocks of the memory system.