IP Library Granted Patent US 11,587,937
Granted Patent B2
US 11,587,937 · App. 17/346,579 · Granted Feb 21, 2023

Method of forming semiconductor device including trimmed-gates

Inventors: Yu-Jen Chen (Hsinchu, TW); Wen-Hsi Lee (Hsinchu, TW); Ling-Sung Wang (Hsinchu, TW); I-Shan Huang (Hsinchu, TW); Chan-Yu Hung (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L27/1104G06F30/39H01L23/528H01L27/0886H01L29/4238H01L29/42376H01L29/785
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Quick Facts
Patent No.
US 11,587,937
App. No.
17/346,579
Granted
Feb 21, 2023
Kind
B2
Abstract

A method (of manufacturing a semiconductor device) includes: forming active regions including spacing apart neighboring active regions resulting in corresponding gaps; forming gate structures (overlying the active regions and the gaps) including locating intra-gap segments of the gate structures over the gaps, arranging each intra-gap segment to include two end regions separated by a central region, and at intersections between active regions and gate structures that is designated to be non-functional (flyover intersection), preventing formation of a functional connection between the two; and removing selected portions of at least some of the intra-gap segments including removing central regions of first selected intra-gap segments substantially without removing portions of corresponding end regions of the first selected intra-gap segments, and removing central regions and portions of end regions of second selected intra-gap segments for which corresponding end regions of the second intra-gap segments abut flyover intersections thereby trimming corresponding gate structures.

Claims (78)

1. A method of manufacturing a semiconductor device, the method comprising:

forming active regions oriented parallel to a first direction, the forming active regions including:

spacing apart neighboring ones of the active regions resulting in corresponding gaps therebetween;

forming gate structures overlying corresponding ones of the active regions and the gaps and being oriented parallel to a second direction, the second direction being orthogonal to the first direction, the forming gate structures including:

locating intra-gap segments of the gate structures correspondingly over the gaps;

arranging each intra-gap segment to include two end regions separated by a central region; and

at an intersection between a corresponding one of the active regions and a corresponding one of the gate structures that is designated to be non-functional (flyover intersection), preventing formation of a functional connection between the corresponding one of the active regions and the corresponding one of the gate structures; and

removing selected portions of at least some of the intra-gap segments including:

removing central regions of first selected ones of intra-gap segments substantially without removing portions of corresponding end regions of the first selected ones of intra-gap segments; and

removing central regions and portions of corresponding end regions of second selected ones of intra-gap segments for which the corresponding end regions of the second selected ones of intra-gap segments abut corresponding flyover intersections thereby trimming corresponding gate structures.

2. The method of claim 1 , wherein the forming active regions further includes:

forming at least one component of a semiconductor integrated circuit (IC) in a corresponding at least one of the active regions.

3. The method of claim 1 , wherein the forming gate structures further includes:

at an intersection between a corresponding one of the active regions and a corresponding one of the gate structures that is designated to be functional (functional intersection), making a functional connection between the corresponding one of the active regions and the corresponding one of the gate structures.

4. The method of claim 3 , wherein:

each of the end regions extends a corresponding overhang distance in the second direction from the corresponding one of the active regions towards the corresponding one of the central regions of the first selected ones of intra-gap segments;;

the first selected ones of intra-gap segments abut corresponding functional intersections; and

for each end region of the first selected ones of intra-gap segments, the corresponding overhang distance is approximately equal to a predetermined value which facilitates the making a functional connection between the corresponding one of the active regions and the corresponding one of the gate structures.

5. The method of claim 4 , wherein:

each of the gate structures has substantially a same width in the first direction; and

the predetermined value is less than or equal to about a three times multiple of the width of the gate structures.

6. The method of claim 4 , wherein:

each of the gate structures has substantially a same width in the first direction; and

the predetermined value is greater than of the width of the gate structures.

7. The method of claim 6 , further comprising:

over locations formerly corresponding to the central regions of the first selected ones of the intra-gap segments, forming one or more metal lines in one or more corresponding metallization layers.

8. The method of claim 7 , wherein:

at least some of the one or more metal lines represent portions of a power grid.

9. A method of manufacturing a semiconductor device, the method comprising:

forming active regions that extend in a first direction, the forming active regions including:

spacing apart neighboring ones of the active regions resulting in corresponding gaps therebetween;

forming gate structures overlying corresponding ones of the active regions and the gaps and being oriented parallel to a second direction, the second direction being orthogonal to the first direction, the forming gate structures including;

locating intra-gap segments of the gate structures correspondingly over the gaps;

arranging each intra-gap segment to include two end regions separated by a central region; and

at an intersection between a corresponding one of the active regions and a corresponding one of the gate structures that is designated to be non-functional (flyover intersection), preventing formation of a functional connection between the corresponding one of the active regions and the corresponding one of the gate structures;

at an intersection between a corresponding one of the active regions and a corresponding one of the gate structures that is designated to be functional (functional intersection), making a functional connection between the corresponding one of the active regions and the corresponding one of the gate structures; and

removing selected portions of at least some of the intra-gap segments including:

removing central regions of first selected ones of the intra-gap segments for which corresponding end regions abut functional intersections substantially without removing portions of corresponding end regions of the first selected ones of intra-gap segments; and

removing central regions and portions of corresponding end regions of second selected ones of the intra-gap segments for which the corresponding end regions of the second selected ones of intra-gap segments abut flyover intersections.

10. The method of claim 9 , wherein the forming active regions further includes:

forming at least one component of a semiconductor integrated circuit in a corresponding at least one of the active regions.

11. The method of claim 9 , wherein:

each of the end regions extends a corresponding overhang distance in the second direction from the corresponding one of the active regions towards the corresponding one of the central regions of the first selected ones of intra-gap segments;

the first selected ones of intra-gap segments abut corresponding functional intersections; and

for each end region of the first selected ones of intra-gap segments, the corresponding overhang distance is approximately equal to a predetermined value which facilitates the making a functional connection between the corresponding one of the active regions and the corresponding one of the gate structures.

12. The method of claim 11 , wherein:

each of the gate structures has substantially a same width in the first direction; and

the predetermined value is greater than of the width of the gate structures.

13. The method of claim 11 , wherein:

each of the gate structures has substantially a same width in the first direction; and

the predetermined value is less than or equal to about a three times multiple of the width of the gate structures.

14. The method of claim 9 , further comprising:

over locations formerly corresponding to the central regions of the first selected ones of the intra-gap segments, forming one or more metal lines in one or more corresponding metallization layers.

15. The method of claim 14 , wherein:

at least some of the one or more metal lines represent portions of a power grid.

16. The method of claim 9 , wherein:

the removing central regions and portions of corresponding end regions of second selected ones of the intra-gap segments for which the corresponding end regions abut flyover intersections substantially completely removes the corresponding end regions so that corresponding gate structures do not extend substantially into the corresponding gaps.

17. A method of manufacturing a semiconductor device, the method comprising:

forming active regions oriented parallel to a first direction, the forming active regions including:

spacing apart neighboring ones of the active regions resulting in corresponding gaps therebetween; and

forming at least one component of a semiconductor integrated circuit (IC) in a corresponding at least one of the active regions;

forming gate structures overlying corresponding ones of the active regions and the gaps and being oriented parallel to a second direction, the second direction being orthogonal to the first direction, the forming gate structures including:

locating intra-gap segments of the gate structures correspondingly over the gaps;

arranging each intra-gap segment to include two end regions separated by a central region; and

at an intersection between a corresponding one of the active regions and a corresponding one of the gate structures that is designated to be non-functional (flyover intersection), preventing formation of a functional connection between the corresponding one of the active regions and the corresponding one of the gate structures;

removing selected portions of at least some of the intra-gap segments including:

removing central regions of first selected ones of intra-gap segments substantially without removing portions of corresponding end regions of the first selected ones of intra-gap segments; and

removing central regions and portions of corresponding end regions of second selected ones of intra-gap segments for which the corresponding end regions of the second selected ones of intra-gap segments abut corresponding flyover intersections; and

over locations formerly corresponding to the central regions of the first selected ones of the intra-gap segments, forming one or more metal lines in one or more corresponding metallization layers.

18. The method of claim 17 , wherein the forming gate structures further includes:

at an intersection between a corresponding one of the active regions and a corresponding one of the gate structures that is designated to be functional (functional intersection), making a functional connection between the corresponding one of the active regions and the corresponding one of the gate structures.

19. The method of claim 18 , wherein:

each of the end regions extends a corresponding overhang distance in the second direction from the corresponding one of the active regions towards the corresponding one of the central regions of the first selected ones of intra-gap segments;

the first selected ones of intra-gap segments abut corresponding functional intersections;

each of the gate structures has substantially a same width in the first direction; and

for each end region of the first selected ones of intra-gap segments, the corresponding overhang distance is approximately equal to a predetermined value which facilitates the making a functional connection between the corresponding one of the active regions and the corresponding one of the gate structures, the predetermined value being greater than of the width of the gate structures and less than or equal to about a three times multiple of the width of the gate structures.

20. The method of claim 17 , wherein:

at least some of the one or more metal lines represent portions of a power grid.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2021
From: CHEN, YU-JEN; LEE, WEN-HSI; WANG, LING-SUNG; HUANG, I-SHAN; HUNG, CHAN-YU
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 056531/0968 →
Continuity (4)
Continuation 16512175 · Jul 15, 2019
Division 15729307 · Oct 10, 2017
Provisional Application 62511488 · May 26, 2017
Related Publication 20210305261A1 · Sep 30, 2021