IP Library Granted Patent US 11,942,429
Granted Patent B2
US 11,942,429 · App. 17/351,811 · Granted Mar 26, 2024

Three-dimensional memory device and method of making thereof using double pitch word line formation

Inventors: Tatsuya Hinoue (Yokkaichi, JP); Naoki Takeguchi (Nagoya, JP); Masanori Tsutsumi (Yokkaichi, JP); Seiji Shimabukuro (Yokkaichi, JP)
Assignee: SANDISK TECHNOLOGIES LLC
H01L23/535H01L21/76805H01L21/76895H01L23/5226H01L23/5329H10B41/27H10B43/27
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,942,429
App. No.
17/351,811
Granted
Mar 26, 2024
Kind
B2
Abstract

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Memory openings, contact via cavities, or backside trenches may be used as access points for removing the sacrificial material layers.

Claims (36)

1. A three-dimensional memory device comprising:

a vertical repetition of multiple instances of a unit layer stack, wherein the unit layer stack comprises, from bottom to top, a first-type insulating layer, a first-type electrically conductive layer comprising a first conductive barrier liner and a first conductive fill material layer, a second-type insulating layer, and a second-type electrically conductive layer comprising a second conductive fill material layer and a second conductive barrier liner;

memory openings vertically extending through the vertical repetition; and

memory opening fill structures located within the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements;

wherein:

the first conductive fill material layer and the second conductive fill material layer are in direct contact with horizontal surfaces of the second-type insulating layer;

the first conductive barrier liner is in direct contact with a horizontal surface of the first-type insulating layer; and

the second conductive barrier liner is in direct contact with a horizontal surface of another first-type insulating layer of an adjacent unit layer stack.

2. The three-dimensional memory device of claim 1 , wherein within each instance of the unit layer stack:

an entirety of a bottom surface of the second-type insulating layer is in direct contact with a top surface of the first conductive fill material layer; and

an entirety of a bottom surface of the second conductive fill material layer is in direct contact with a top surface of the second-type insulating layer.

3. The three-dimensional memory device of claim 1 , wherein, within each instance of the unit layer stack:

an entirety of a bottom surface of the first conductive fill material layer is in direct contact with a top surface of the first conductive barrier liner; and

an entirety of a bottom surface of the second conductive barrier liner is in direct contact with a top surface of the second conductive fill material layer.

4. The three-dimensional memory device of claim 1 , wherein each instance of the first conductive fill material layer and the second conductive fill material layer has a same conductive fill material composition and a same conductive fill material thickness.

5. The three-dimensional memory device of claim 4 , wherein each instance of the first conductive barrier liner and the second conductive barrier liner has a same conductive liner composition and a same conductive liner thickness.

6. The three-dimensional memory device of claim 1 , wherein within each instance of the unit layer stack:

the first-type insulating layer comprises a seamless insulating layer that is free of any seam therein; and

the second-type insulating layer comprises a seamed insulating layer including a horizontally-extending seam therein.

7. The three-dimensional memory device of claim 6 , wherein each of the memory opening fill structures is laterally spaced from each horizontally-extending seam by a respective seamless portion of the seamed insulating layer.

8. The three-dimensional memory device of claim 6 , wherein the horizontally-extending seam within the seamed insulating layer in each instance of the unit layer stack is equidistant from a horizontal interface between the seamed insulating layer and the second-type electrically conductive layer, and from a horizontal interface between the seamed insulating layer and the first-type electrically conductive layer.

9. The three-dimensional device of claim 6 , further comprising:

a first backside trench fill structure comprising a first dielectric surface contacting first sidewalls of each layer within the vertical repetition and laterally extending along a first horizontal direction; and

a second backside trench fill structure comprising a second dielectric surface contacting second sidewalls of each layer within a first vertical repetition of the vertical repetition of multiple instances, laterally extending along the first horizontal direction, and laterally spaced from the first backside trench fill structure along a second horizontal direction.

10. The three-dimensional memory device of claim 9 , wherein:

each of the first backside trench fill structure and the second backside trench fill structure has a respective laterally-undulating vertical cross-sectional profile in the second horizontal direction; and

each of the first backside trench fill structure and the second backside trench fill structure has a greater width at levels of each of the first-type electrically conductive layer, seamless insulating layer, and second-type electrically conductive than at levels of each seamed insulating layer.

11. The three-dimensional memory device of claim 9 , wherein each horizontally-extending seam within each seamed insulating layer is in direct contact with a respective one of the first dielectric surface and the second dielectric surface.

12. The three-dimensional memory device of claim 9 , wherein each of the first backside trench fill structure and the second backside trench fill structure comprises:

a backside contact via structure contacting a respective source region in a substrate; and

an insulating spacer laterally surrounding the backside contact via structure and comprising a respective one of the first dielectric surface and the second dielectric surface as an outer surface.

13. The three-dimensional memory device of claim 6 , wherein the seamed insulating layer comprises an air gap encapsulated by a dielectric material layer having an upper horizontally-extending portion and a lower horizontally-extending portion that are adjoined to each other at a periphery of the air gap at the horizontally-extending seam.

14. The three-dimensional memory device of claim 1 , further comprising:

a retro-stepped dielectric material portion overlying stepped surfaces of the vertical repetition;

first-type contact via structures vertically extending through the retro-stepped dielectric material portion and contacting a top surface of a respective instance of the first-type electrically conductive layer; and

second-type contact via structures vertically extending through the retro-stepped dielectric material portion and contacting a top surface of a respective instance of the second-type electrically conductive layer.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2021
From: HINOUE, TATSUYA; TAKEGUCHI, NAOKI; TSUTSUMI, MASANORI; SHIMABUKURO, SEIJI
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 056603/0081 →
Continuity (1)
Related Publication 20220406720A1 · Dec 22, 2022