Binary metallic alloy source and drain (BMAS) for applying compressive stress in non-planar transistor architectures
Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a semiconductor device comprises a semiconductor channel, a source region adjacent to the semiconductor channel, and a drain region adjacent to the semiconductor channel. In an embodiment, the source region and the drain region each comprise a trench, a conformal silicide lining the trench, and a binary metallic alloy filling the trench.
1 . A semiconductor device, comprising:
a semiconductor channel;
a source region adjacent to the semiconductor channel; and
a drain region adjacent to the semiconductor channel, wherein the source region and the drain region each comprise:
a trench in the semiconductor channel;
a conformal silicide layer lining the trench; and
a binary metallic alloy filling the trench, wherein the binary metallic alloy is configured to apply a compressive stress to the semiconductor channel based on being annealed with a capping layer disposed over the trench.
2 . The semiconductor device of claim 1 , wherein binary metallic alloy comprises a host element and a seed element.
3 . The semiconductor device of claim 2 , wherein the host element comprises titanium or tantalum.
4 . The semiconductor device of claim 2 , wherein the seed element comprises hafnium, tin, or zirconium.
5 . The semiconductor device of claim 1 , wherein the conformal silicide semiconductor layer has a thickness of approximately 10 nm or smaller.
6 . The semiconductor device of claim 1 , wherein the semiconductor device is a non-planar transistor.
7 . The semiconductor device of claim 6 , wherein the non-planar transistor is a fin-FET transistor.
8 . The semiconductor device of claim 6 , wherein the non-planar transistor is a gate-all-around (GAA) transistor.
9 . A method of forming a semiconductor device, the method comprising:
forming a semiconductor channel;
forming a source region adjacent to the semiconductor channel;
forming a drain region adjacent to the semiconductor channel, and wherein the forming the source region and the drain region comprises:
forming a trench in the semiconductor channel;
conformally growing a semiconductor layer along the surfaces of the trench;
filling the trench with a host metal;
disposing a capping layer over the trench;
implanting a seed metal into the host metal through the capping layer; and
annealing the semiconductor device, wherein the annealing forms a binary metallic alloy comprising the host metal and the seed metal and converts the semiconductor layer to a conformal silicide layer lining the trench, and wherein the binary metallic alloy fills the trench and is configured to apply a compressive stress to the semiconductor channel based on the annealing with the capping layer disposed over the trench.
10 . The method of claim 9 , wherein a composition of the binary alloy comprises approximately 90 atomic percent or more of the host metal.
11 . The method of claim 9 , wherein the host metal comprises titanium or tantalum.
12 . The semiconductor device of claim 9 , wherein the seed element comprises hafnium, tin, or zirconium.
13 . The method of claim 9 , wherein the semiconductor layer has a thickness that is approximately 10 nm or smaller.
14 . The method of claim 9 , wherein the semiconductor device is a fin-FET device or a gate-all-around (GAA) device.
15 . An electronic system, comprising:
a board;
a die coupled to the package substrate, wherein the die comprises a semiconductor device comprising:
a semiconductor channel;
a source region adjacent to the semiconductor channel; and
a drain region adjacent to the semiconductor channel, wherein the source region and the drain region each comprise:
a trench in the semiconductor channel;
a conformal silicide layer lining the trench; and
a binary metallic alloy filling the trench, wherein the binary metallic alloy is configured to apply a compressive stress to the semiconductor channel based on being annealed with a capping layer disposed over the trench.
16 . The electronic system of claim 15 , wherein the semiconductor device is a fin-FET device or a gate-all-around (GAA) device.