Semiconductor device including stack structure and trenches
A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
1. A semiconductor device comprising:
a substrate having a first surface and a second surface facing each other;
a first main block and a second main block on the first surface of the substrate;
a first dummy block and a second dummy block on the first surface of the substrate;
a main trench between the first main block and the second main block; and
a dummy trench between a portion of the first dummy block and a portion of the second dummy block,
wherein each of the first and second main blocks includes:
main insulating layers and main conductive material layers, which are alternately and repeatedly stacked, and
cell pillars penetrating through the main insulating layers and the main conductive material layers in a vertical direction perpendicular to the first surface of the substrate,
wherein each of the first and second dummy blocks includes:
dummy insulating layers and dummy conductive material layers, which are alternately and repeatedly stacked;
a lower mold layer between the substrate and a lowermost dummy conductive material layer of the dummy conductive material layers, wherein a material of the lower mold layer is different from a material of each of the main conductive material layers and the dummy conductive material layers; and
dummy pillars penetrating through the dummy insulating layers, the dummy conductive material layers, and the lower mold layer in the vertical direction,
wherein the first and second main blocks are adjacent to each other in a first direction parallel to the first surface of the substrate,
wherein the first and second dummy blocks are adjacent to each other in the first direction, and
wherein the lower mold layer of each of the first and second dummy blocks is substantially same level as a lowermost main conductive material layer of the main conductive material layers.
2. The semiconductor device of claim 1 ,
wherein each of the main trench and the dummy trench extends in a second direction parallel to the first surface of the substrate, and
wherein the second direction is perpendicular to the first direction.
3. The semiconductor device of claim 2 ,
wherein a width of the main trench in the first direction is greater than a width of the dummy trench in the first direction.
4. The semiconductor device of claim 1 ,
wherein the lower mold layer of the first dummy block and the lower mold layer of the second dummy block extend between a lower surface of the dummy trench and the first surface of the substrate.
5. The semiconductor device of claim 1 ,
wherein a lower end of the dummy trench is spaced apart from the substrate and is at a higher level than the first surface of the substrate, and
wherein the main trench extends in the substrate.
6. The semiconductor device of claim 1 ,
wherein a distance between the dummy trench and the second surface of the substrate is greater than a distance between the main trench and the second surface of the substrate.
7. The semiconductor device of claim 1 ,
wherein an uppermost main conductive material layer of the main conductive material layers is substantially at the same level as an uppermost dummy conductive material layer of the dummy conductive material layers,
wherein the lowermost dummy conductive material layer of the dummy conductive material layers is at a higher level than the lowermost main conductive material layer, and
wherein the lower mold layer is between the lowermost dummy conductive material layer and the substrate.
8. The semiconductor device of claim 1 ,
wherein the material of the lower mold layer is an insulating material having an etch selectivity with the dummy insulating layers.
9. The semiconductor device of claim 1 , further comprising:
a bit line on the first main block, the second main block, the first dummy block, and the second dummy block; and
bit plugs disposed between the bit line and the cell pillars, but not between the bit line and the dummy pillars,
wherein each of the cell pillars and the dummy pillars includes a core pattern, a channel pattern on a side surface of the core pattern, and an information storage pattern of an external side surface of the channel pattern.
10. The semiconductor device of claim 1 , further comprising:
a main pattern in the main trench; and
a dummy pattern in the dummy trench,
wherein each of the main pattern and the dummy pattern includes a conductive material line and an insulating spacer on a sidewall of the conductive material line.
11. A semiconductor device comprising:
a substrate having a first surface and a second surface facing each other;
a plurality of blocks on the first surface of the substrate and including a first block, a second block, and a third block; and
a plurality of trenches including a first trench adjacent to the first block, a second trench adjacent to the second block, and a third trench adjacent to the third block,
wherein the plurality of blocks are sequentially arranged in a first direction parallel to the first surface of the substrate,
wherein the first block includes:
first insulating layers and first conductive material layers, which are alternately and repeatedly stacked, and
first pillars penetrating through the first insulating layers and the first conductive material layers in a vertical direction perpendicular to the first surface of the substrate,
wherein the second block includes:
second insulating layers and second conductive material layers, which are alternately and repeatedly stacked, and
second pillars penetrating through the second insulating layers and the second conductive material layers in the vertical direction,
wherein an uppermost first conductive material layer of the first conductive material layers and an uppermost second conductive material layer of the second conductive material layers are substantially at the same level,
wherein an upper end of the first trench and an upper end of the second trench are at the higher level than the uppermost first conductive material layer,
wherein a lowermost end of the first trench and a lowermost end of the second trench are at different levels from each other,
wherein each of plurality of trenches extends in a second direction parallel to the first surface of the substrate, and
wherein the second direction is perpendicular to the first direction.
12. The semiconductor device of claim 11 ,
wherein the first trench and the second trench are sequentially arranged in the first direction, and
wherein the lower end of the first trench is at a lower level than the lower end of the second trench.
13. The semiconductor device of claim 11 ,
wherein the lower end of the first trench is at a lower level than a lowermost first conductive material layer of the first conductive material layers, and
wherein the lower end of the second trench is at a lower level than a lowermost second conductive material layer of the second conductive material layers.
14. The semiconductor device of claim 11 ,
wherein a width of the first trench in the first direction is greater than a width of the second trench in the first direction.
15. The semiconductor device of claim 11 , further comprising:
a first pattern in the first trench; and
a second pattern in the second trench,
wherein each of the first and second patterns includes a conductive material line and an insulating spacer on a sidewall of the conductive material line.
16. The semiconductor device of claim 11 ,
wherein the third block includes:
third insulating layers and third conductive material layers, which are alternately and repeatedly stacked, and
third pillars penetrating through the third insulating layers and the third conductive material layers in the vertical direction,
wherein an uppermost third conductive material layer of the third conductive material layers is substantially at the same level as the uppermost first conductive material layer of the first conductive material layers,
wherein an upper end of the third trench is at the higher level than the uppermost first conductive material layer,
wherein the first trench, the second trench and the third trench are sequentially arranged in the first direction,
wherein the lower end of the first trench is at a lower level than a lowermost first conductive material layer of the first conductive material layers,
wherein the lower end of the second trench is at a lower level than a lowermost second conductive material layer of the second conductive material layers, and
wherein the lower end of the third trench is at a lower level than a lowermost third conductive material layer of the third conductive material layers.
17. A semiconductor device comprising:
a substrate having a first surface and a second surface facing each other;
a plurality of blocks on the first surface of the substrate and including a main block and a dummy block;
a plurality of trenches including a main trench adjacent to the main block and a dummy trench adjacent to the dummy block,
wherein the plurality of blocks are sequentially arranged in a first direction parallel to the first surface of the substrate,
wherein the main block includes:
main insulating layers and main conductive material layers, which are alternately and repeatedly stacked, and
cell pillars penetrating through the main insulating layers and the main conductive material layers in a vertical direction perpendicular to the first surface of the substrate,
wherein the dummy block includes:
dummy insulating layers and dummy conductive material layers, which are alternately and repeatedly stacked;
a lower mold layer between the substrate and a lowermost dummy conductive material layer of the dummy conductive material layers; and
dummy pillars penetrating through the dummy insulating layers, the dummy conductive material layers, and the lower mold layer in the vertical direction
wherein an uppermost main conductive material layer of the main conductive material layers is substantially at the same level as an uppermost dummy conductive material layer of the dummy conductive material layers,
wherein an upper end of the main trench and an upper end of the dummy trench are at the higher level than the uppermost main conductive material layer,
wherein a lowermost main conductive material layer of the main conductive material layers is substantially at the same level as the lower mold layer of the dummy block, and
wherein a lowermost end of the main trench is at a lower level than a lowermost end of the dummy trench.
18. The semiconductor device of claim 17 ,
wherein the lower mold layer extends between the first surface of the substrate and a lower surface of the dummy trench, and
wherein the lower end of the main trench is at a lower level than the lower end of the dummy trench.
19. The semiconductor device of claim 17 ,
wherein each of the main trench and the dummy trench extends in a second direction parallel to the first surface of the substrate,
wherein the second direction is perpendicular to the first direction,
wherein a width of the main trench in the first direction is greater than a width of the dummy trench in the first direction.
20. The semiconductor device of claim 17 , further comprising:
a main pattern in the main trench; and
a dummy pattern in the dummy trench,
wherein each of the main pattern and the dummy pattern includes a conductive material line and an insulating spacer on a sidewall of the conductive material line.