One selector one resistor MRAM crosspoint memory array fabrication methods
A memory array is provided that includes a plurality of word lines and a plurality of bit lines, and a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element. Each memory cell is coupled between one of the word lines and one of the bit lines. Each memory cell has a half-pitch F, and comprises an area between 2F 2 and 4F 2 .
1. A memory array comprising:
a plurality of word lines and a plurality of bit lines; and
a plurality of memory cells each comprising a corresponding magnetic memory element coupled in series with a corresponding selector element, and each of the plurality of memory cells is coupled in series with a corresponding via having four concave vertical sidewalls, each memory cell coupled between one of the word lines and one of the bit lines, each memory cell comprising a half-pitch F, wherein each memory cell comprises an area between 2F 2 and 4F 2 .
2. The memory array of claim 1 , wherein each memory cell is vertically-oriented.
3. The memory array of claim 1 , comprising a cross-point memory array.
4. The memory array of claim 1 , comprising a first layer of memory cells, and a second layer of memory cells disposed above the first layer of memory cells.
5. The memory array of claim 1 , wherein the word lines are arranged in a first direction, and the bit lines are arranged in a second direction perpendicular to the first direction.
6. The memory array of claim 1 , wherein the memory cells are disposed above the word lines, and the bit lines are disposed above the memory cells.
7. The memory array of claim 1 , wherein the memory cells are disposed above the bit lines, and the word lines are disposed above the memory cells.
8. The memory array of claim 1 , wherein each of the vias coupled between one of the word lines and one of the bit lines.
9. The memory array of claim 8 , wherein each of a first plurality of the vias is disposed above a corresponding one of a first plurality of the memory cells, and each of a second plurality of the vias is disposed below a corresponding one of a second plurality of the memory cells.
10. The memory array of claim 1 , comprising a first memory level, and a second memory level disposed above the first memory level.
11. The memory array of claim 10 , wherein the first memory level and the second memory level share one of the plurality of word lines and the plurality of bit lines.
12. The memory array of claim 1 , wherein each selector element comprises one or more of a threshold selector device, a conductive bridge threshold selector device, an ovonic threshold switch, and a Metal Insulator Transition of a Phase Transition Material type threshold selector device.
13. The memory array of claim 1 , wherein each selector element comprises one or more of SiTe, CTe, BTe, AlTe, SiAsTe, GeAsSe, GeAsSeSi, VO 2 , and NbO 2 .
14. The memory array of claim 1 , wherein each selector element comprises HfOx doped with one or more of Cu, Ag, or similar metallic ion.
15. A method of forming a memory array, the method comprising: forming a plurality of first memory cells each comprising a corresponding first magnetic memory element coupled in series with a corresponding first selector element; and forming a plurality of first vias between adjacent first memory cells, wherein each memory cell comprises a half-pitch F, and comprises an area between 2F 2 and 4F 2 , wherein each of the plurality of first vias comprises four concave vertical sidewalls.
16. The method of claim 15 , further comprising: forming a plurality of second memory cells each comprising a corresponding second magnetic memory element coupled in series with a corresponding second selector element; and forming a plurality of second vias between adjacent second memory cells.
17. The method of claim 16 , wherein each second memory cell is disposed over a corresponding one of the first vias, and each first memory cell is disposed under a corresponding one of the second vias.
18. The method of claim 15 , wherein each first selector element comprises one or more of a threshold selector device, a conductive bridge threshold selector device, an ovonic threshold switch, and a Metal Insulator Transition of a Phase Transition Material type threshold selector device.
19. A memory array comprising: a first memory level comprising a plurality of first memory cells each comprising a corresponding magnetic memory element coupled in series with a corresponding selector element, each first memory cell coupled to and disposed above or below a corresponding one of a plurality of first vias each having four concave vertical sidewalls; and a second memory level disposed above the first memory level, the second memory level comprising a plurality of second memory cells each comprising a corresponding magnetic memory element coupled in series with a corresponding selector element, each second memory cell coupled to and disposed above or below a corresponding one of a plurality of second vias each having four concave vertical sidewalls, wherein each memory cell comprises a half-pitch F, and comprises an area between 2F 2 and 4F 2 .
20. The memory array of claim 19 , wherein each selector element comprises one or more of a threshold selector device, a conductive bridge threshold selector device, an ovonic threshold switch, and a Metal Insulator Transition of a Phase Transition Material type threshold selector device.