IP Library › Granted Patent US 12,526,985

Granted Patent B2

US 12,526,985 · App. 17/355,449 · Granted Jan 13, 2026

Back-side reveal for power delivery to backend memory with frontend transistors and backend memroy cells

Inventors: Abhishek A. Sharma (Hillsboro, OR); Wilfred Gomes (Portland, OR); Van H. Le (Beaverton, OR); Kimin Jun (Portland, OR); Hui Jae Yoo (Hillsboro, OR)

Assignee: Intel Corporation

H10B12/50 H01L24/29 H01L24/32 H01L24/83 H01L25/0657 H01L25/50 H10B12/02 H10B12/31 H01L2224/29187 H01L2224/32146 H01L2924/1436

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Quick Facts

Patent No.: US 12,526,985
App. No.: 17/355,449
Granted: Jan 13, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Embodiments of the present disclosure provide power to backend memory of an IC device from the back side of the device. An example IC device with back-side power delivery for backend memory includes a frontend layer with a plurality of frontend components such as frontend transistors, a backend layer (that may include a plurality of layers) with backend memory (e.g., with one or more eDRAM arrays), and a back-side power delivery structure with a plurality of back-side interconnects electrically coupled to the backend memory, where the frontend layer is between the back-side power delivery structure and the backend layer.

Claims (86)

1 . An integrated circuit (IC) device, comprising:

a first IC structure, comprising:

a first layer comprising transistors, and

a second layer comprising memory cells;

a second IC structure comprising a third layer comprising further memory cells; and

a structure comprising interconnects, wherein:

the first layer is between the second layer and the structure,

the second layer is between the first layer and the third layer,

at least one of the interconnects is coupled to one or more of the memory cells,

at least one of the interconnects is coupled to one or more of the further memory cells,

each of the first IC structure, the second IC structure, and the structure includes a first face and a second face opposite the first face,

the IC device further includes a bonding interface between the first face of the second IC structure and the first face of the first IC structure,

the IC device further includes a conductive via extending from the second face of the second IC structure to the at least one of the interconnects that is coupled to the one or more of the further memory cells,

the first face of the structure is closer to the second face of the first IC structure than the second face of the structure,

in a plane that is substantially perpendicular to the bonding interface, each of a cross-section of the conductive via and a cross-section of at least one of the interconnects is substantially a polygon having a first side and a second side substantially parallel to the first side and longer than the first side,

for the polygon of the cross-section of the conductive via, the first side is closer to the second face of the structure than the second side, and

for the polygon of the cross-section of at least one of the interconnects, the second side is closer to the second face of the structure than the first side.

2 . The IC device according to claim 1 , wherein the conductive via extends through the second IC structure, through the bonding interface, and into the first IC structure.

3 . The IC device according to claim 1 , wherein the at least one of the interconnects is coupled to the one or more of the further memory cells by being coupled to the conductive via and the conductive via being coupled to the one or more of the further memory cells.

4 . The IC device according to claim 1 , wherein the first face of the structure is closer to the bonding interface than the second face of the structure.

5 . The IC device according to claim 1 , wherein:

each of the first IC structure and the second IC structure includes a first face and a second face opposite the first face,

the first IC structure includes first additional interconnects,

the second IC structure includes second additional interconnects,

in the plane that is substantially perpendicular to the bonding interface, each of a cross-section of at least one of the first additional interconnects and a cross-section of at least one of the second additional interconnects is substantially a polygon having a first side and a second side substantially parallel to the first side and longer than the first side,

for the polygon of the cross-section of the at least one of the first additional interconnects, the first side is closer to the second face of the structure than the second side, and

for the polygon of the cross-section of the at least one of the second additional interconnects, the second side is closer to the second face of the structure than the first side.

6 . The IC device according to claim 5 , wherein:

a direction of a taper of the conductive via is same as a direction of a taper of the at least one of the first additional interconnects and opposite to a direction of a taper of the at least one of the interconnects and to a direction of a taper of the at least one of the second additional interconnects.

7 . The IC device according to claim 1 , wherein:

each of the first IC structure and the second IC structure includes a first face and a second face opposite the first face,

the first IC structure includes first additional interconnects,

the second IC structure includes second additional interconnects,

for the polygon of the cross-section of the at least one of the first additional interconnects, the first side is closer to the second face of the structure than the second side, and

for the polygon of the cross-section of the at least one of the second additional interconnects, the first side is closer to the second face of the structure than the second side.

8 . The IC device according to claim 7 , wherein:

a direction of a taper of the conductive via is opposite to a direction of a taper of the at least one of the interconnects and same as a direction of a taper of the at least one of the first additional interconnects and a direction of a taper of the at least one of the second additional interconnects.

9 . The IC device according to claim 1 , wherein the IC device is an IC package, and wherein the IC package further includes a component coupled to at least one of the first IC structure, the second IC structure, or the structure.

10 . The IC device according to claim 9 , wherein the component includes one of a package substrate, an interposer, or an IC die.

11 . An integrated circuit (IC) device, comprising:

a first IC structure comprising a first layer comprising transistors and a second layer comprising memory cells;

a second IC structure comprising a third layer comprising further memory cells; and

a structure comprising interconnects, wherein:

the first layer is between the second layer and the structure,

the second layer is between the first layer and the third layer,

at least one of the interconnects is coupled to one or more of the memory cells,

at least one of the interconnects is coupled to one or more of the further memory cells,

each of the first IC structure, the second IC structure, and the structure includes a first face and a second face opposite the first face,

the IC device further includes a bonding interface between the first face of the second IC structure and the first face of the first IC structure,

the first face of the structure is closer to the second face of the first IC structure than the second face of the structure,

in a plane that is substantially perpendicular to the bonding interface, each of a cross-section of the conductive via and a cross-section of at least one of the interconnects is substantially a trapezoid having a first side and a second side substantially parallel to the first side and longer than the first side,

for the trapezoid of the cross-section of the conductive via, the first side is closer to the second face of the structure than the second side, and

for the trapezoid of the cross-section of at least one of the interconnects, the second side is closer to the second face of the structure than the first side.

12 . The IC device according to claim 11 , wherein the first face of the structure is closer to the bonding interface than the second face of the structure.

13 . The IC device according to claim 11 , wherein:

each of the first IC structure and the second IC structure includes a first face and a second face opposite the first face,

the first IC structure includes first additional interconnects,

the second IC structure includes second additional interconnects,

for the polygon of the cross-section of the at least one of the first additional interconnects, the first side is closer to the second face of the structure than the second side, and

for the polygon of the cross-section of the at least one of the second additional interconnects, the second side is closer to the second face of the structure than the first side.

14 . The IC device according to claim 11 , wherein:

each of the first IC structure and the second IC structure includes a first face and a second face opposite the first face,

the first IC structure includes first additional interconnects,

the second IC structure includes second additional interconnects,

for the polygon of the cross-section of the at least one of the first additional interconnects, the first side is closer to the second face of the structure than the second side, and

for the polygon of the cross-section of the at least one of the second additional interconnects, the first side is closer to the second face of the structure than the second side.

15 . The IC device according to claim 11 , wherein the IC device is an IC package, and wherein the IC package further includes a component coupled to at least one of the first IC structure, the second IC structure, or the structure.

16 . The IC device according to claim 15 , wherein the component includes one of a package substrate, an interposer, or an IC die.

17 . An integrated circuit (IC) device, comprising:

an IC structure comprising a first layer comprising transistors and a second layer comprising memory cells; and

a structure comprising interconnects, wherein:

the first layer is between the second layer and the structure,

at least one of the interconnects is coupled to one or more of the memory cells,

the IC structure further includes additional interconnects,

each of the IC structure and the structure includes a first face and a second face opposite the first face,

the first face of the IC structure is closer to the second face of the structure than the second face of the IC structure,

the second face of the structure is closer to the second face of the IC structure than the first face of the structure,

the IC device further includes a conductive via extending from the second face of the IC structure to the at least one of the interconnects that is coupled to one or more of the memory cells, and

in a cross-section of the IC device in a plane that is substantially perpendicular to the first layer, the conductive via tapers in a direction from the second face of the structure to the first face of the structure and at least one of the interconnects tapers in a direction opposite to the direction from the second face of the structure to the first face of the structure.

18 . The IC device according to claim 17 , wherein, in the cross-section of the IC device in the plane that is substantially perpendicular to the first layer, at least one of the additional interconnects tapers in the direction from the second face of the structure to the first face of the structure.

19 . The IC device according to claim 17 , wherein the IC device is an IC package, and wherein the IC package further includes a component coupled to at least one of the IC structure or the structure.

20 . The IC device according to claim 19 , wherein the component includes one of a package substrate, an interposer, or an IC die.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2021

From: SHARMA, ABHISHEK A.; GOMES, WILFRED; LE, VAN H; JUN, KIMIN; YOO, HUI JAE

To: INTEL CORPORATION

Reel/Frame 056955/0536 →

Continuity (1)

Related Publication 20220415904A1 · Dec 29, 2022

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