Three-dimensional memory arrays with layer selector transistors
A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
1. An integrated circuit (IC) device, comprising:
a first arrangement that includes two or more memory cells, a first transistor, and a first wordline;
a second arrangement that includes two or more memory cells, a second transistor, and a second wordline; and
an interconnect structure,
wherein:
each memory cell of the first arrangement and the second arrangement includes an access transistor,
a gate electrode of the access transistor of each of the two or more memory cells of the first arrangement is coupled to the first wordline, and the first wordline is coupled to a first source or drain (S/D) region of the first transistor,
a gate electrode of the access transistor of each of the two or more memory cells of the second arrangement is coupled to the second wordline, and the second wordline is coupled to a first S/D region of the second transistor, and
each of a second S/D region of the first transistor and a second S/D region of the second transistor is coupled to the interconnect structure.
2. The IC device according to claim 1 , wherein:
the first arrangement further includes a first local interconnect structure, and
a gate electrode of the first transistor is coupled to the first local interconnect structure.
3. The IC device according to claim 2 , wherein:
the first arrangement further includes two or more further memory cells, a further first transistor, and a further first wordline,
each memory cell of the two or more further memory cells of the first arrangement includes an access transistor,
a gate electrode of the access transistor of each of the two or more further memory cells of the first arrangement is coupled to the further first wordline,
the further first wordline is coupled to a first S/D region of the further first transistor, and
a gate electrode of the further first transistor is coupled to the first local interconnect structure.
4. The IC device according to claim 3 , wherein:
the interconnect structure is a first interconnect structure,
the IC device further includes a second interconnect structure,
a second S/D region of the further first transistor is coupled to the second interconnect structure.
5. The IC device according to claim 4 , wherein:
the second arrangement further includes two or more further memory cells, a further second transistor, and a further second wordline,
each memory cell of the two or more further memory cells of the second arrangement includes an access transistor,
a gate electrode of the access transistor of each of the two or more further memory cells of the second arrangement is coupled to the further second wordline, and the further second wordline is coupled to a first S/D region of the further second transistor, and
a second S/D region of the further second transistor is coupled to the second interconnect structure.
6. The IC device according to claim 5 , wherein:
the second arrangement further includes a second local interconnect structure, and
a gate electrode of the further second transistor is coupled to the second local interconnect structure.
7. The IC device according to claim 5 , wherein:
the first arrangement further includes an additional first transistor and a first bitline,
a second arrangement further includes an additional second transistor and a second bitline,
the IC device further includes an additional interconnect structure, a first S/D region of the access transistor of each of one of the two or more memory cells of the first arrangement and one of the two or more further memory cells of the first arrangement is coupled to the first bitline,
the first bitline is coupled to a first S/D region of the additional first transistor,
a first S/D region of the access transistor of each of one of the two or more memory cells of the second arrangement and one of the two or more further memory cells of the second arrangement is coupled to the second bitline,
the second bitline is coupled to a first S/D region of the additional second transistor, and
each of a second S/D region of the additional first transistor and a second S/D region of the additional second transistor is coupled to the additional interconnect structure.
8. The IC device according to claim 1 , wherein:
the IC device further includes a support structure,
the first arrangement is in a first layer above the support structure,
the second arrangement is in a second layer above the support structure, where the
first layer is between the support structure and the second layer, and
the interconnect structure is a via extending between the first layer and the second layer.
9. The IC device according to claim 1 , wherein at least one of the first transistor and the second transistor is a thin film transistor (TFT).
10. The IC device according to claim 9 , wherein the TFT includes a channel material that includes one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, indium gallium zinc oxide (IGZO), indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, and black phosphorus.
11. An integrated circuit (IC) package, comprising:
an IC device; and
a further component, coupled to the IC device, wherein the IC device includes:
a first arrangement that includes two or more memory cells, a first transistor, and a first wordline;
a second arrangement that includes two or more memory cells, a second transistor, and a second wordline; and
an interconnect structure,
wherein:
each memory cell of the first arrangement and the second arrangement includes an access transistor,
a gate electrode of the access transistor of each of the two or more memory cells of the first arrangement is coupled to the first wordline, and the first wordline is coupled to a first source or drain (S/D) region of the first transistor,
a gate electrode of the access transistor of each of the two or more memory cells of the second arrangement is coupled to the second wordline, and the second wordline is coupled to a first S/D region of the second transistor, and
each of a second S/D region of the first transistor and a second S/D region of the second transistor is coupled to the interconnect structure.
12. The IC package according to claim 11 , wherein:
the first arrangement further includes a first local interconnect structure, and
a gate electrode of the first transistor is coupled to the first local interconnect structure.
13. The IC package according to claim 12 , wherein:
the first arrangement further includes two or more further memory cells, a further first transistor, and a further first wordline,
each memory cell of the two or more further memory cells of the first arrangement includes an access transistor,
a gate electrode of the access transistor of each of the two or more further memory cells of the first arrangement is coupled to the further first wordline,
the further first wordline is coupled to a first S/D region of the further first transistor, and
a gate electrode of the further first transistor is coupled to the first local interconnect structure.
14. The IC package according to claim 13 , wherein:
the interconnect structure is a first interconnect structure,
the IC device further includes a second interconnect structure,
a second S/D region of the further first transistor is coupled to the second interconnect structure.
15. The IC package according to claim 11 , wherein the further component is a package substrate or an interposer.
16. A computing device, comprising:
a processing device; and
a memory device, coupled to the processing device, wherein the processing device or the memory device comprises an integrated circuit (IC) device that includes:
a first arrangement that includes two or more memory cells, a first transistor, and a first wordline;
a second arrangement that includes two or more memory cells, a second transistor, and
a second wordline; and
an interconnect structure,
wherein:
each memory cell of the first arrangement and the second arrangement includes an access transistor,
a gate electrode of the access transistor of each of the two or more memory cells of the first arrangement is coupled to the first wordline, and the first wordline is coupled to a first source or drain (S/D) region of the first transistor,
a gate electrode of the access transistor of each of the two or more memory cells of the second arrangement is coupled to the second wordline, and the second wordline is coupled to a first S/D region of the second transistor, and
each of a second S/D region of the first transistor and a second S/D region of the second transistor is coupled to the interconnect structure.
17. The computing device according to claim 16 , wherein:
the first arrangement further includes a first local interconnect structure, and
a gate electrode of the first transistor is coupled to the first local interconnect structure.
18. The computing device according to claim 17 , wherein:
the first arrangement further includes two or more further memory cells, a further first transistor, and a further first wordline,
each memory cell of the two or more further memory cells of the first arrangement includes an access transistor,
a gate electrode of the access transistor of each of the two or more further memory cells of the first arrangement is coupled to the further first wordline,
the further first wordline is coupled to a first S/D region of the further first transistor, and
a gate electrode of the further first transistor is coupled to the first local interconnect structure.
19. The computing device according to claim 16 , wherein the computing device is a handheld or a wearable computing device.
20. The computing device according to claim 16 , further comprising a battery or a power circuit.