Field programmable multichip package based on field-programmable-gate-array (FPGA) integrated-circuit (IC) chip
A semiconductor IC chip comprising: a silicon substrate; a first transistor at a top surface of the silicon substrate; a first through silicon via (TSV) vertically in the silicon substrate; a second through silicon via (TSV) vertically in the silicon substrate; a first interconnection scheme on the top surface of the silicon substrate, wherein the first interconnection scheme comprises an insulating dielectric layer, a metal via in the insulating dielectric layer, a metal pad on a bottom surface of the insulating dielectric layer and a bottom surface of the metal via and coupling to the first TSV, and a first metal interconnect coupling the second TSV to the first transistor; and a second interconnection scheme on a bottom surface of the silicon substrate, wherein the second interconnection scheme comprises a second metal interconnect coupling the first TSV to the second TSV; and a first metal contact at a top of the semiconductor IC chip and on a top surface of the first interconnection scheme, wherein the first metal contact couples to the first transistor through, in sequence, the metal via, metal pad, first TSV, second metal interconnect, second TSV and first metal interconnect, wherein the first metal contact is configured for coupling to a voltage of power supply.
1 . A semiconductor integrated-circuit (IC) chip comprising:
a silicon layer;
a first transistor having a portion in the silicon layer;
a first interconnection scheme over a top surface of the silicon layer and over the first transistor, wherein the first interconnection scheme comprises:
a first insulating dielectric layer,
a first interconnection metal layer extending on a top surface of the first insulating dielectric layer and further extending downwards into an opening in the first insulating dielectric layer, wherein the first interconnection metal layer comprises a first copper layer having a sidewall over the top surface of the first insulating dielectric layer and a first adhesion metal layer at a bottom of the first copper layer and at the sidewall of the first copper layer,
a second interconnection metal layer over the first interconnection metal layer, and
a second insulating dielectric layer between the first and second interconnection metal layers;
a second interconnection scheme for power and ground distribution, wherein the second interconnection scheme is under a bottom surface of the silicon layer and comprises:
a third insulating dielectric layer,
a third interconnection metal layer extending on a bottom surface of the third insulating dielectric layer and further extending upwards into an opening in the third insulating dielectric layer, wherein the third interconnection metal layer comprises a second copper layer having a sidewall under the bottom surface of the third insulating dielectric layer and a second adhesion metal layer at a top of the second copper layer and at the sidewall of the second copper layer,
a fourth insulating dielectric layer under the third interconnection metal layer, and
a fourth interconnection metal layer extending on a bottom surface of the fourth insulating dielectric layer and further extending upwards into an opening in the fourth insulating dielectric layer, wherein the fourth interconnection metal layer comprises a conductive metal layer having a sidewall under the bottom surface of the fourth insulating dielectric layer and a third adhesion metal layer at a top of the conductive metal layer and not at the sidewall of the conductive metal layer;
a first metal via between the first and second interconnection schemes and in contact with the second interconnection scheme, wherein the second interconnection scheme couples to the first transistor through the first metal via; and
a first metal contact at a bottom of the semiconductor integrated-circuit (IC) chip and under and in contact with the second interconnection scheme, wherein the first metal contact couples to the first transistor through, in sequence, the second interconnection scheme and first metal via.
2 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the second interconnection scheme comprises a power distribution network coupling the first metal contact to the first metal via.
3 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the second interconnection scheme comprises a ground distribution network coupling the first metal contact to the first metal via.
4 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first metal via comprises a copper via having a width in a horizontal direction between 0.05 and 0.5 micrometers and a thickness in a vertical direction between 0.3 and 10 micrometers.
5 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the second copper layer has a thickness in a vertical direction between 0.05 and 1 micrometers.
6 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first metal contact comprises a metal bump containing tin.
7 . The semiconductor integrated-circuit (IC) chip of claim 1 is a central-processing-unit (CPU) integrated-circuit (IC) chip.
8 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first metal via has a maximum transverse dimension smaller than 0.1 micrometers.
9 . The semiconductor integrated-circuit (IC) chip of claim 1 is a graphic-processing-unit (GPU) integrated-circuit (IC) chip.
10 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first metal via couples to the first transistor through the first interconnection scheme.
11 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first metal via is at a same horizontal level as the first transistor.
12 . The semiconductor integrated-circuit (IC) chip of claim 3 further comprising:
a second transistor having a portion in the silicon layer;
a second metal contact at the bottom of the semiconductor integrated-circuit (IC) chip and under and in contact with the second interconnection scheme; and
a second metal via between the first and second interconnection schemes, in contact with the second interconnection scheme and coupling the second interconnection scheme to the second transistor, wherein the second interconnection scheme further comprises a power distribution network coupling the second metal contact to the second metal via.
13 . The semiconductor integrated-circuit (IC) chip of claim 1 further comprising
a second transistor having a portion in the silicon layer; and
a second metal via between the first and second interconnection schemes and in contact with the second interconnection scheme, wherein the first metal contact couples to the second transistor through, in sequence, the second interconnection scheme and second metal via.
14 . The semiconductor integrated-circuit (IC) chip of claim 1 further comprising a second metal via between the first and second interconnection schemes and in contact with the second interconnection scheme, wherein the first interconnection scheme comprises a first metal interconnect coupling the first metal via to the second metal via, and wherein the second interconnection scheme comprises a second metal interconnect coupling the first metal via to the second metal via.
15 . The semiconductor integrated-circuit (IC) chip of claim 1 further comprising a second transistor having a portion in the silicon layer, wherein the first interconnection scheme comprises a signal interconnect coupling to the second transistor.
16 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the conductive metal layer comprises a third copper layer.
17 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the third adhesion metal layer comprises titanium.
18 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein each of the first, second and third interconnection metal layers comprises a metal trace having a thickness between 0.05 and 2 micrometers.
19 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the fourth interconnection metal layer comprises a metal trace having a thickness between 0.5 and 10 micrometers.
20 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the fourth interconnection metal layer has a thickness greater than that of each of the first and second interconnection metal layers.
21 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein each of the first, second and third insulating dielectric layers comprises silicon oxide.
22 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the fourth insulating dielectric layer comprises silicon oxynitride.
23 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first interconnection scheme comprises a first insulating bonding layer over the second interconnection metal layer and at a top of the first interconnection scheme, wherein the first insulating bonding layer is configured to be bonded to an external element, wherein the external element comprises a silicon substrate and a second insulating bonding layer under the silicon substrate, at a bottom of the external element and bonded to and in contact with the first insulating bonding layer, wherein each of the first and second insulating bonding layers comprises silicon.
24 . The semiconductor integrated-circuit (IC) chip of claim 23 , wherein the first insulating bonding layer comprises silicon oxide.
25 . The semiconductor integrated-circuit (IC) chip of claim 23 , wherein the first insulating bonding layer comprises silicon oxynitride.
26 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the second interconnection scheme comprises a fifth insulating dielectric layer under the fourth interconnection metal layer and at a bottom of the semiconductor integrated-circuit (IC) chip, wherein the first metal contact extends on a bottom surface of the fifth insulating dielectric layer and further extends upwards into an opening in the fifth insulating dielectric layer and in contact with a bottom surface of the fourth interconnection metal layer.
27 . The semiconductor integrated-circuit (IC) chip of claim 26 , wherein the first metal contact comprises a third copper layer extending under the bottom surface of the fifth insulating dielectric layer and further extending upwards into the opening in the fifth insulating dielectric layer.
28 . The semiconductor integrated-circuit (IC) chip of claim 27 , wherein the first metal contact further comprises a tin-containing cap under the third copper layer.
29 . The semiconductor integrated-circuit (IC) chip of claim 26 , wherein the fifth insulating dielectric layer comprises a polymer layer.
30 . The semiconductor integrated-circuit (IC) chip of claim 1 further comprising an oxide layer therein, wherein the first metal via extends through the oxide layer.
31 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first transistor is a gate-all-around field effective transistor (GAAFET).
32 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first transistor is a fin field effective transistor (FINFET).