Packages with Si-substrate-free interposer and method forming same
A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.
1. A method comprising:
forming a plurality of dielectric layers;
forming a plurality of redistribution lines in the plurality of dielectric layers;
etching the plurality of dielectric layers to form an opening;
filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers;
forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers;
forming a plurality of bond pads in the dielectric layer;
bonding a first device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding;
encapsulating the first device die in a dielectric material, with the dielectric material having a bottom surface contacting a top surface of the dielectric layer and a second portion of the plurality of bond pads, wherein the first portion and the second portion of the plurality of bond pads are different portions separated from each other;
bonding a second device die to the first device die;
forming a first oxide layer over and in physical contacting a semiconductor material of a semiconductor substrate of the second device die;
forming a first bond pad extending into the first oxide layer;
forming a second bond pad and a second oxide layer on a blank substrate; and
performing a hybrid bonding to bond the first bond pad to the second bond pad, and the first oxide layer to the second oxide layer.
2. The method of claim 1 further comprising bonding a third device die to the dielectric layer and a third portion of the plurality of bond pads through hybrid bonding, wherein the plurality of redistribution lines connects the first device die to the third device die.
3. The method of claim 1 further comprising:
forming a through-via in the dielectric material, wherein the through-via is in physical contact with one of the second portion of the plurality of bond pads.
4. The method of claim 1 further comprising:
polishing an additional semiconductor substrate of the first device die to reveal surfaces of through-silicon vias in the first device die; and
bonding the second device die directly to the through-silicon vias.
5. The method of claim 1 , wherein the first bond pad extends into the semiconductor substrate of the second device die, and a bottom surface of the first bond pad is at an intermediate level between a top surface and a bottom surface of the semiconductor substrate.
6. The method of claim 1 , wherein the first bond pad contacts, without extending into, the semiconductor substrate of the second device die, and wherein all sidewall surfaces of the first bond pad are in contact with the first oxide layer.
7. The method of claim 1 , wherein the first bond pad forms a grid.
8. The method of claim 1 , wherein the forming the plurality of dielectric layers comprises:
forming a plurality of low-k dielectric layers; and
forming a plurality of etch stop layers, wherein the opening formed by the etching the plurality of dielectric layers penetrates through the plurality of low-k dielectric layers and the plurality of etch stop layers.
9. A method comprising:
forming a plurality of dielectric layers;
forming a plurality of redistribution lines in each of the plurality of dielectric layers;
forming a first through-dielectric via and a second through-dielectric via penetrating through the plurality of dielectric layers;
forming a dielectric layer over the plurality of dielectric layers;
forming a plurality of bond pads in the dielectric layer and electrically coupling to the first through-dielectric via, the second through-dielectric via, and the plurality of redistribution lines;
bonding a first device die and a second device die to the dielectric layer and the plurality of bond pads through hybrid bonding, wherein the first device die and the second device die are electrically interconnected through the plurality of redistribution lines;
filling a gap-filling material on opposite sides the first device die and the second device die;
forming a third through-dielectric via penetrating through the gap-filling material; and
bonding a third device die directly to, and in physical contact with, the third through-dielectric via; and
bonding a die stack to the second device die.
10. The method of claim 9 , wherein the plurality of redistribution lines is formed using damascene processes.
11. The method of claim 9 further comprising forming a fourth through-dielectric via penetrating through the gap-filling material, wherein the second device die is bonded directly to, and in physical contact with, the third through-dielectric via, and the die stack is bonded directly to, and in physical contact with, the fourth through-dielectric via.
12. The method of claim 9 , wherein the forming the first through-dielectric via and the second through-dielectric via comprises:
etching the plurality of dielectric layers to form a first opening and a second opening; and
filling the first opening and the second opening with a conductive material.
13. The method of claim 9 further comprising:
thinning the first device die and the second device die to expose through-silicon vias in the first device die and the second device die; and
bonding a third device die to the through-silicon vias.
14. The method of claim 13 further comprising:
forming a dielectric layer over the third device die; and
bonding a bulk wafer to the dielectric layer.
15. A package comprising:
a plurality of dielectric layers;
a plurality of redistribution lines in each of the plurality of dielectric layers;
a first through-dielectric via penetrating through the plurality of dielectric layers;
a plurality of bond pads over and connected to the first through-dielectric via and the plurality of redistribution lines;
a first dielectric layer, with the plurality of bond pads located in the first dielectric layer;
a first device die bonded to the first dielectric layer and a first portion of the plurality of bond pads through hybrid bonding;
a gap-filling material on opposite sides of the first device die;
a second through-dielectric via penetrating through the gap-filling material; and
a die stack bonded to the second through-dielectric via.
16. The package of claim 15 further comprising a second device die bonded to the first dielectric layer and a second portion of the plurality of bond pads through hybrid bonding, wherein the first device die and the second device die are electrically coupled to each other through the plurality of redistribution lines.
17. The package of claim 15 further comprising:
a second device die over and bonded to the first device die;
a bond pad contacting a semiconductor substrate of the second device die, wherein at least a portion of the bond pad is over the semiconductor substrate of the second device die;
a second dielectric layer, with the bond pad having at least a portion in the second dielectric layer; and
a bulk substrate over and bonded to the second dielectric layer and the bond pad.
18. The package of claim 17 , wherein the bulk substrate is formed of silicon, and no active device and passive device is formed on the bulk substrate.
19. The package of claim 17 , wherein the bond pad further extends into the semiconductor substrate of the second device die.
20. The package of claim 17 , wherein the bond pad forms a grid.