Multi-output look-up table (LUT) for use in coarse-grained field-programmable-gate-array (FPGA) integrated-circuit (IC) chip
A semiconductor integrated-circuit (IC) chip comprises a memory cell including: a latch circuit comprising first and second inverters coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter; a first N-type MOS transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first output point of the memory cell, and a first gate terminal for controlling coupling between the first latch node and the first output point of the memory cell; a second N-type MOS transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second output point of the memory cell, and a second gate terminal for controlling coupling between the second latch node and the second output point of the memory cell; and a P-type MOS transistor having a fifth terminal coupling to the first latch node, a sixth terminal coupling to a third output point of the memory cell, and a third gate terminal for controlling coupling between the first latch node and the third output point of the memory cell.
1. A multichip package comprising:
an interconnection scheme;
a first metal bump under and coupling to the interconnection scheme and at a bottom of the multichip package;
a semiconductor integrated-circuit (IC) chip over the interconnection scheme and coupling to the first metal bump through the interconnection scheme, wherein the semiconductor integrated-circuit (IC) chip is field-programmable; and
a non-volatile memory (NVM) integrated-circuit (IC) chip over the interconnection scheme, wherein the non-volatile memory (NVM) integrated-circuit (IC) chip comprises a first data terminal coupling to a first data terminal of the semiconductor integrated-circuit (IC) chip through the interconnection scheme and a read-enable terminal coupling to a first input/output (I/O) terminal of the semiconductor integrated-circuit (IC) chip through the interconnection scheme, wherein the semiconductor integrated-circuit (IC) chip is configured to control the non-volatile memory (NVM) integrated-circuit (IC) chip and load first configuration data from the non-volatile memory (NVM) integrated-circuit (IC) chip to the semiconductor integrated-circuit (IC) chip when the multichip package is powered on, wherein the semiconductor integrated-circuit (IC) chip is configured to pass a read-enable signal from the first input/output (I/O) terminal of the semiconductor integrated-circuit (IC) chip to the read-enable terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip to activate the first data terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip for passing the first configuration data from the first data terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip to the first data terminal of the semiconductor integrated-circuit (IC) chip for configuring the semiconductor integrated-circuit (IC) chip in accordance with data associated with the first configuration data, wherein the read-enable terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip and the first input/output (I/O) terminal of the semiconductor integrated-circuit (IC) chip are coupled to each other through a first path starting from the first input/output (I/O) terminal of the semiconductor integrated-circuit (IC) chip to the read-enable terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip, wherein the first path is completely buried in one or more insulating dielectric materials of the multichip package and has no electrical contact at all surfaces of the multichip package.
2. The multichip package of claim 1 , wherein the first data terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip and the first data terminal of the semiconductor integrated-circuit (IC) chip are coupled to each other through a second path starting from the first data terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip to the first data terminal of the semiconductor integrated-circuit (IC) chip, wherein the second path is completely buried in said one or more insulating dielectric materials of the multichip package and has no electrical contact at said all surfaces of the multichip package.
3. The multichip package of claim 1 , wherein the semiconductor integrated-circuit (IC) chip further comprises a second data terminal coupling to a second data terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip through the interconnection scheme and a second input/output (I/O) terminal coupling to a write-enable terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip through the interconnection scheme, wherein the semiconductor integrated-circuit (IC) chip is configured to pass a write-enable signal from the second input/output (I/O) terminal of the semiconductor integrated-circuit (IC) chip to the write-enable terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip to activate the second data terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip for passing second configuration data from the second data terminal of the semiconductor integrated-circuit (IC) chip to the second data terminal of the non-volatile memory (NVM) integrated-circuit (IC) chip, wherein the non-volatile memory (NVM) integrated-circuit (IC) chip is configured to store third configuration data associated with the second configuration data therein.
4. The multichip package of claim 3 , wherein the semiconductor integrated-circuit (IC) chip is configured to receive fourth configuration data from a circuit external of the multichip package, wherein the second configuration data is associated with the fourth configuration data.
5. The multichip package of claim 1 , wherein the semiconductor integrated-circuit (IC) chip comprises a memory cell configured to store second configuration data therein associated with the first configuration data and a selection circuit having a first set of input points for a first input data set for a logic operation and a second set of input points for a second input data set having data associated with the second configuration data, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data for the logic operation.
6. The multichip package of claim 1 , wherein the semiconductor integrated-circuit (IC) chip comprises a first and a second metal interconnect, a memory cell configured to store second configuration data therein associated with the first configuration data, and a switch circuit having a first point coupling to the first metal interconnect, a second point coupling to the second metal interconnect and a third point for input data associated with the second configuration data, wherein the switch is configured to control, in accordance with the input data at the third point, coupling between the first and second metal interconnects.
7. The multichip package of claim 1 , wherein a first bond is provided between the semiconductor integrated-circuit (IC) chip and interconnection scheme to join the semiconductor integrated-circuit (IC) chip and interconnection scheme, wherein the first bond is coupled to the first metal bump through the interconnection scheme, wherein the first path comprises a second bond provided between the semiconductor integrated-circuit (IC) chip and interconnection scheme to join the semiconductor integrated-circuit (IC) chip and interconnection scheme, a third bond provided between the non-volatile memory (NVM) integrated-circuit (IC) chip and interconnection scheme to join the non-volatile memory (NVM) integrated-circuit (IC) chip and interconnection scheme and a metal interconnect of the interconnection scheme coupling the second bond to the third bond, wherein the second and third bonds and metal interconnect are completely buried in said one or more insulating dielectric materials of the multichip package and has no electrical contact at said all surfaces of the multichip package.
8. The multichip package of claim 1 comprising a chip package having the non-volatile memory (NVM) integrated-circuit (IC) chip therein, wherein the chip package comprises a second metal bump at a bottom thereof bonded to a top of the interconnection scheme.
9. The multichip package of claim 1 comprising a first chip package having the semiconductor integrated-circuit (IC) chip therein and a second chip package having the non-volatile memory (NVM) integrated-circuit (IC) chip therein and over the first chip package, wherein the first chip package comprises a second metal bump at a bottom thereof boned to a top of the interconnection scheme, and the second chip package comprises a third metal bump at a bottom thereof bonded to a top of the first chip package.
10. The multichip package of claim 1 further comprising a molding compound on the interconnection scheme, at a same horizontal level as the semiconductor integrated circuit (IC) chip and non-volatile memory (NVM) integrated-circuit (IC) chip and between the semiconductor integrated circuit (IC) chip and non-volatile memory (NVM) integrated-circuit (IC) chip.
11. The multichip package of claim 1 , wherein the first metal bump comprises a tin-containing bump.
12. The multichip package of claim 1 is a field-programmable application-specific integrated-circuit (ASIC) chip package.
13. The multichip package of claim 1 , wherein the semiconductor integrated-circuit (IC) chip is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
14. The multichip package of claim 1 , wherein the semiconductor integrated-circuit (IC) chip is an embedded field-programmable-gate-array (e-FPGA) integrated-circuit (IC) chip.
15. A multichip package comprising:
an interconnection scheme;
a first metal bump under and coupling to the interconnection scheme and at a bottom of the multichip package;
a semiconductor integrated-circuit (IC) chip over the interconnection scheme, wherein the semiconductor integrated-circuit (IC) chip comprises a first data terminal coupling to the first metal bump through the interconnection scheme, wherein the first data terminal of the semiconductor integrated-circuit (IC) chip is configured to receive first configuration data from the first metal bump for configuring the semiconductor integrated-circuit (IC) chip in accordance with data associated with the first configuration data; and
a non-volatile memory (NVM) integrated-circuit (IC) chip over the interconnection scheme, wherein the non-volatile memory (NVM) integrated-circuit (IC) chip comprises a data terminal coupling to a second data terminal of the semiconductor integrated-circuit (IC) chip through the interconnection scheme for receiving second configuration data associated with the first configuration data, wherein the non-volatile memory (NVM) integrated-circuit (IC) chip is configured to store third configuration data associated with the second configuration data therein.
16. The multichip package of claim 15 , wherein the third configuration data is kept in the non-volatile memory (NVM) integrated-circuit (IC) chip when the multichip package is powered off, and wherein the semiconductor integrated-circuit (IC) chip is configured to control the non-volatile memory (NVM) integrated-circuit (IC) chip and load fourth configuration data from the non-volatile memory (NVM) integrated-circuit (IC) chip to the semiconductor integrated-circuit (IC) chip when the multichip package is powered on, wherein the fourth configuration data is associated with the third configuration data.
17. The multichip package of claim 15 , wherein the semiconductor integrated-circuit (IC) chip comprises a memory cell configured to store fourth configuration data therein associated with the first configuration data and a selection circuit having a first set of input points for a first input data set for a logic operation and a second set of input points for a second input data set having data associated with the fourth configuration data, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data for the logic operation.
18. The multichip package of claim 15 , wherein the semiconductor integrated-circuit (IC) chip comprises a first and a second metal interconnect, a memory cell configured to store fourth configuration data therein associated with the first configuration data, and a switch circuit having a first point coupling to the first metal interconnect, a second point coupling to the second metal interconnect and a third point for input data associated with the fourth configuration data, wherein the switch circuit is configured to control, in accordance with the input data at the third point, coupling between the first and second metal interconnects.
19. The multichip package of claim 15 comprising a chip package having the non-volatile memory (NVM) integrated-circuit (IC) chip therein, wherein the chip package comprises a second metal bump at a bottom thereof bonded to a top of the interconnection scheme.
20. The multichip package of claim 15 comprising a first chip package having the semiconductor integrated-circuit (IC) chip therein and a second chip package having the non-volatile memory (NVM) integrated-circuit (IC) chip therein and over the first chip package, wherein the first chip package comprises a second metal bump at a bottom thereof bonded to a top of the interconnection scheme, and the second chip package comprises a third metal bump at a bottom thereof bonded to a top of the first chip package.
21. The multichip package of claim 15 further comprising a molding compound on the interconnection scheme, at a same horizontal level as the semiconductor integrated circuit (IC) chip and non-volatile memory (NVM) integrated-circuit (IC) chip and between the semiconductor integrated circuit (IC) chip and non-volatile memory (NVM) integrated-circuit (IC) chip.
22. The multichip package of claim 15 , wherein the first metal bump comprises a tin-containing bump.
23. The multichip package of claim 15 is a field-programmable application-specific integrated-circuit (ASIC) chip package.
24. The multichip package of claim 15 , wherein the semiconductor integrated-circuit (IC) chip is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
25. The multichip package of claim 15 , wherein the semiconductor integrated-circuit (IC) chip is an embedded field-programmable-gate-array (e-FPGA) integrated-circuit (IC) chip.