Bonding pad architecture using capacitive deep trench isolation (CDTI) structures for electrical connection
A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.
1. A method, comprising:
forming a plurality of capacitive deep trench isolation structures extending completely through a semiconductor substrate from a front side surface to a back side surface, each capacitive deep trench isolation structure comprising a conductive region insulated from the semiconductor substrate by an insulating liner;
providing a metallization structure at the front side surface of the semiconductor substrate that is electrically connected to first ends of the plurality of capacitive deep trench isolation structures;
recessing the back side surface of the semiconductor substrate to expose second ends of the plurality of capacitive deep trench isolation structures; and
forming a bonding pad structure adjacent the recessed back side surface of the semiconductor substrate, wherein the bonding pad structure is directly physically and electrically connected to the conductive regions at the second ends of the plurality of capacitive deep trench isolation structures and electrically insulated from the semiconductor substrate, wherein forming the bonding pad structure comprises:
depositing a conformal layer of a dielectric material on the recessed back side surface and exposed second ends of the plurality of capacitive deep trench isolation structures;
depositing a conformal layer of an oxide material on the layer of the dielectric material;
planarizing the layer of the oxide material;
opening an aperture extending through at least the layer of the dielectric material which extends on end surfaces of the plurality of capacitive deep trench isolation structures to expose the conductive regions at the second ends of the plurality of capacitive deep trench isolation structures; and
depositing one or more metal materials forming the bonding pad structure within said aperture.
2. The method of claim 1 , wherein planarizing the layer of oxide material comprises stopping planarization at the layer of the dielectric material, and wherein opening the aperture comprises opening the aperture to extend through the layer of the dielectric material.
3. The method of claim 1 , wherein planarizing the layer of the oxide material comprises stopping planarization before reaching the layer of the dielectric material, and wherein opening the aperture comprises opening the aperture to extend through both the layer of the oxide material and the layer of the dielectric material.
4. The method of claim 1 , wherein the semiconductor substrate includes a core area and a peripheral area, and wherein recessing the back side surface of the semiconductor substrate is performed in the peripheral area but not in the core area.
5. A method, comprising:
forming a plurality of capacitive deep trench isolation structures extending completely through a semiconductor substrate from a front side surface to a back side surface, each capacitive deep trench isolation structure comprising a conductive region insulated from the semiconductor substrate by an insulating liner;
providing a metallization structure at the front side surface of the semiconductor substrate that is electrically connected to first ends of the plurality of capacitive deep trench isolation structures;
recessing the back side surface of the semiconductor substrate to expose second ends of first capacitive deep trench isolation structures of said plurality of capacitive deep trench isolation structures; and
forming a bonding pad structure adjacent the recessed back side surface of the semiconductor substrate, wherein the bonding pad structure is directly physically and electrically connected to the conductive regions at the second ends of the first capacitive deep trench isolation structures and electrically insulated from the semiconductor substrate, wherein forming the bonding pad structure comprises:
depositing a conformal layer of a dielectric material on the recessed back side surface and exposed second ends of the first capacitive deep trench isolation structures;
depositing a conformal layer of an oxide material on the layer of the dielectric material;
planarizing the layer of the oxide material;
opening an aperture extending through at least the layer of the dielectric material which extends on end surfaces of the first capacitive deep trench isolation structures to expose the conductive regions at the second ends of the first capacitive deep trench isolation structures; and
depositing one or more metal materials forming the bonding pad structure within said aperture.
6. The method of claim 5 , wherein planarizing the layer of the oxide material comprises stopping planarization at the layer of the dielectric material, and wherein opening the aperture comprises opening the aperture to extend through the layer of the dielectric material.
7. The method of claim 5 , wherein planarizing the layer of the oxide material comprises stopping planarization before reaching the layer of the dielectric material, and wherein opening the aperture comprises opening the aperture to extend through both the layer of the oxide material and the layer of the dielectric material.
8. The method of claim 5 , wherein the semiconductor substrate includes a core area and a peripheral area, wherein said first capacitive deep trench isolation structures are located in the peripheral area, said plurality of capacitive deep trench isolation structures further including second capacitive deep trench isolation structures located in the core area, and wherein recessing the back side surface of the semiconductor substrate is performed in the peripheral area but not in the core area.
9. The method of claim 8 , further comprising forming a photosensitive circuit in the core area of the semiconductor substrate, said photosensitive circuit delimited by said second capacitive deep trench isolation structures.
10. The method of claim 9 , further comprising placing a lens over the photosensitive circuit above the planarized layer of the oxide material.
11. The method of claim 5 , wherein the semiconductor substrate includes a core area and a peripheral area, wherein said first capacitive deep trench isolation structures are located in the peripheral area, said plurality of capacitive deep trench isolation structures further including second capacitive deep trench isolation structures located in the core area, and wherein recessing the back side surface of the semiconductor substrate is performed in both the peripheral area and the core area so as to expose second ends of the second capacitive deep trench isolation structures.
12. The method of claim 11 , wherein the layer of the dielectric material is deposited on the exposed second ends of the second capacitive deep trench isolation structures, and wherein forming the bonding pad structure further comprises:
opening a further aperture extending through at least the layer of the dielectric material which extends on end surfaces of the plurality of capacitive deep trench isolation structures to expose the conductive regions at the second ends of the first capacitive deep trench isolation structures; and
depositing one or more metal materials forming the bonding pad structure within said further aperture.
13. The method of claim 12 , wherein planarizing the layer of the oxide material comprises stopping planarization at the layer of the dielectric material, and wherein opening the aperture comprises opening the aperture to extend through the layer of the dielectric material.
14. The method of claim 12 , wherein planarizing the layer of the oxide material comprises stopping planarization before reaching the layer of the dielectric material, and wherein opening the aperture comprises opening the aperture to extend through both the layer of the oxide material and the layer of the dielectric material.
15. The method of claim 11 , further comprising forming a photosensitive circuit in the core area of the semiconductor substrate, said photosensitive circuit delimited by said second capacitive deep trench isolation structures.
16. The method of claim 15 , further comprising placing a lens over the photosensitive circuit above the planarized layer of the oxide material.