Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.
1 . A multi-chip package comprising:
an interconnection scheme comprising:
a first interconnection metal layer,
a first polymer layer over the first interconnection metal layer,
a second interconnection metal layer extending horizontally on a top surface of the first polymer layer and further extending downwards into a first opening in the first polymer layer, wherein the second interconnection metal layer comprises a first copper layer extending horizontally over the top surface of the first polymer layer and further extending downwards into the first opening in the first polymer layer, wherein the first copper layer has a sidewall over the top surface of the first polymer layer, wherein the second interconnection metal layer further comprises a first adhesion metal layer at a bottom of the first copper layer and not at the sidewall of the first copper layer,
a second polymer layer on the second interconnection metal layer and first polymer layer and at a top of the interconnection scheme, and
a plurality of first metal bumps each at the top of the interconnection scheme, extending horizontally on a top surface of the second polymer layer, further extending downwards into a second opening in the second polymer layer and in contact with a top surface of the second interconnection metal layer, wherein each of the plurality of first metal bumps comprises a second copper layer extending horizontally over the top surface of the second polymer layer and further extending downwards into the second opening in the second polymer layer, wherein the second copper layer has a sidewall over the top surface of the second polymer layer, wherein said each of the plurality of first metal bumps further comprises a second adhesion metal layer at a bottom of the second copper layer, on the top surface of the second polymer layer and the top surface of the second interconnection metal layer and not at the sidewall of the second copper layer;
a third polymer layer under the first interconnection scheme and at a bottom of the multi-chip package;
a second metal bump at the bottom of the multi-chip package, extending on a bottom surface of the third polymer layer, further extending upwards into a third opening in the third polymer layer and in contact with a bottom surface of the first interconnection metal layer, wherein the second metal bump comprises a third copper layer extending under the bottom surface of the third polymer layer and further extending upwards into the third opening in the third polymer layer, wherein the third copper layer has a sidewall under the bottom surface of the third polymer layer, wherein the second metal bump further comprises a third adhesion metal layer at a top of the third copper layer and not at the sidewall of the third copper layer, wherein the third adhesion metal layer is between the third copper layer and the bottom surface of third polymer layer, between the third copper layer and the bottom surface of first interconnection metal layer and on the bottom surface of the third polymer layer and the bottom surface of the first interconnection metal layer, wherein the second metal bump further comprises a first tin-containing cap under the third copper layer;
a plurality of semiconductor integrated-circuit (IC) chips over the interconnection scheme and at a same horizontal level as each other or one another, wherein each of the plurality of semiconductor integrated-circuit (IC) chips comprises a third metal bump at a bottom of said each of the plurality of semiconductor integrated-circuit (IC) chips and protruding from a bottom surface of said each of the plurality of semiconductor integrated-circuit (IC) chips, wherein the third metal bump is bonded to one of the plurality of first metal bumps as a bonded contact, wherein the third metal bump comprises a fourth copper layer and a second tin- containing cap under the fourth copper layer and bonded to said one of the plurality of first metal bumps; and
a fourth polymer layer on the interconnection scheme and at the same horizontal level as the plurality of semiconductor integrated-circuit (IC) chips.
2 . The multi-chip package of claim 1 further comprising a metal interconnect extending vertically in the fourth polymer layer for vertical interconnection, wherein the metal interconnect is on the interconnection scheme and at the same horizontal level as the plurality of semiconductor integrated-circuit (IC) chips and the fourth polymer layer.
3 . The multi-chip package of claim 2 is configured for a package-on-package assembly, wherein the package-on-package assembly comprises a chip package bonded to a top of the multi-chip package of the package-on-package assembly, wherein the chip package comprises another semiconductor integrated-circuit (IC) chip therein.
4 . The multi-chip package of claim 2 , wherein the metal interconnect is on a top surface of one of the plurality of first metal bumps.
5 . The multi-chip package of claim 1 , wherein the second copper layer has a thickness between 1 and 60 micrometers.
6 . The multi-chip package of claim 1 , wherein the first second adhesion metal layer comprises titanium.
7 . The multi-chip package of claim 1 , wherein the fourth polymer layer has a sidewall vertically coplanar with a sidewall of the interconnection scheme.
8 . The multi-chip package of claim 1 , wherein the interconnection scheme further comprises a fifth polymer layer under the first polymer layer, wherein the first interconnection metal layer extends horizontally on a top surface of the fifth polymer layer and further extends downwards into a fourth opening in the fifth polymer layer, wherein the third polymer layer is under and on a bottom surface of the fifth polymer layer and the third opening in the third polymer layer is vertically under the fourth opening in the fifth polymer layer, and wherein the second metal bump is under the fourth opening in the fifth polymer layer and in contact with the bottom surface of the first interconnection metal layer at a bottom of the fourth opening in the fifth polymer layer.
9 . The multi-chip package of claim 8 , wherein the first interconnection metal layer comprises a fifth copper layer extending horizontally over the top surface of the fifth polymer layer and further extending downwards into the fourth opening in the fifth polymer layer, wherein the fifth copper layer has a sidewall over the top surface of the fifth polymer layer, and wherein the first interconnection metal layer further comprises a fourth adhesion metal layer between the fifth copper layer and fifth polymer layer, on the top surface of the fifth polymer layer and not at the sidewall of the fifth copper layer.
10 . The multi-chip package of claim 9 , wherein the fourth adhesion metal layer of the first interconnection metal layer is further between the fifth copper layer of the first interconnection metal layer and the third adhesion metal layer of the second metal bump and on a top surface of the third adhesion metal layer of the second metal bump.
11 . The multi-chip package of claim 1 , wherein the first copper layer has a thickness between 0.3 and 20 micrometers.
12 . The multi-chip package of claim 1 , wherein the third adhesion metal layer comprises titanium.
13 . The multi-chip package of claim 1 , wherein said each of the plurality of semiconductor integrated-circuit (IC) chips has a top surface coplanar with a top surface of the fourth polymer layer.
14 . The multi-chip package of claim 1 further comprising an underfill between the interconnection scheme and said each of the plurality of semiconductor integrated-circuit (IC) chips and in contact with a sidewall of the bonded contact.
15 . The multi-chip package of claim 1 , wherein the plurality of semiconductor integrated-circuit (IC) chips comprise a first semiconductor integrated-circuit (IC) chip and a first logic chip coupling to the first semiconductor integrated-circuit (IC) chip.
16 . The multi-chip package of claim 15 , wherein the first semiconductor integrated-circuit (IC) chip is a control chip.
17 . The multi-chip package of claim 15 , wherein the first logic chip is a graphic processing unit (GPU) chip.
18 . The multi-chip package of claim 15 , wherein the first semiconductor integrated-circuit (IC) chip is a memory chip.
19 . The multi-chip package of claim 15 , wherein the first semiconductor integrated-circuit (IC) chip is an input/output (I/O) chip.
20 . The multi-chip package of claim 15 , wherein the first logic chip is a central processing unit (CPU) chip.
21 . The multi-chip package of claim 15 , wherein the first logic chip is a graphic processing unit (GPU) chip and the first semiconductor integrated-circuit (IC) chip is a control chip.
22 . The multi-chip package of claim 15 , wherein the first logic chip is a graphic processing unit (GPU) chip and the first semiconductor integrated-circuit (IC) chip is a memory chip.
23 . The multi-chip package of claim 15 , wherein communication between the first logic chip and first semiconductor integrated-circuit (IC) chip has a data bit width equal to or greater than 1,024.
24 . The multi-chip package of claim 15 , wherein the plurality of semiconductor integrated-circuit (IC) chips further comprises a second semiconductor integrated-circuit (IC) chip and a second logic chip coupling to the second semiconductor integrated-circuit (IC) chip.