Micro heat pipe for use in semiconductor IC chip package
A micro heat transfer component includes a bottom metal plate; a top metal plate; a plurality of sidewalls each having a top end joining the top metal plate and a bottom end joining the bottom metal plate, wherein the top and bottom metal plates and the sidewalls form a chamber in the micro heat transfer component; a plurality of metal posts in the chamber and between the top and bottom metal plates, wherein each of the metal posts has a top end joining the top metal plate and a bottom end joining the bottom metal plate; a metal layer in the chamber, between the top and bottom metal plates and intersecting each of the metal posts, wherein a plurality of openings are in the metal layer, wherein a first space in the chamber is between the metal layer and bottom metal plate and a second space in the chamber is between the metal layer and top metal plate; and a liquid in the first space in the chamber.
1 . A chip package comprising:
a circuit substrate;
a plurality of first solder balls at a bottom of the chip package and under the circuit substrate;
a sub-system package over the circuit substrate, wherein the sub-system package comprises:
a first interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer and an insulating dielectric layer between the first and second interconnection metal layers,
a first metal bump at a bottom of the sub-system package, under and coupling to the first interconnection scheme and bonded to the circuit substrate,
a first integrated-circuit (IC) chip over and coupling to the first interconnection scheme, and
a second integrated-circuit (IC) chip over and coupling to the first integrated-circuit (IC) chip; and
an optical module over the circuit substrate, wherein the optical module comprises:
a second interconnection scheme,
a plurality of second solder balls at a bottom of the optical module, under the second interconnection scheme and coupling to the circuit substrate, and
an optical chip over and coupling to the second interconnection scheme, wherein the optical chip comprises a silicon layer and an optical waveguide having a portion in the silicon layer and the optical chip further comprises an insulating layer on a top surface of the silicon layer and over the optical waveguide, wherein the optical waveguide is configured to be coupled to an optical fiber by a first optical signal, wherein the optical fiber is configured to transmit the first optical signal from above the insulating layer to the optical waveguide under the insulating layer.
2 . The chip package of claim 1 , wherein the first metal bump comprises tin.
3 . The chip package of claim 1 , wherein the first second interconnection metal layer has a copper layer and an adhesion metal layer at a top of the copper layer and not at a sidewall of the copper layer, wherein the copper layer has a thickness between 0.3 and 20 micrometers.
4 . The chip package of claim 1 further comprising a first insulating bonding layer at a top of the first integrated-circuit (IC) chip and a first copper pad in an opening in the first insulating bonding layer and at the top of the first integrated-circuit (IC) chip, wherein the second integrated-circuit (IC) chip comprises a second insulating bonding layer at a bottom of the second integrated-circuit (IC) chip and bonded to the first insulating bonding layer and a second copper pad in an opening in the second insulating bonding layer, at the bottom of the second integrated-circuit (IC) chip and bonded to the first copper pad.
5 . The chip package of claim 1 , wherein the second integrated-circuit (IC) chip comprises a second metal bump at a bottom of the second integrated-circuit (IC) chip and over and coupling to the first integrated-circuit (IC) chip, wherein the second metal bump comprises a first tin-containing cap at its bottom.
6 . The chip package of claim 5 , wherein the second metal bump further comprises a copper layer over the first tin-containing cap and with a thickness between 1 and 20 micrometers.
7 . The chip package of claim 5 , wherein the first integrated-circuit (IC) chip further comprises a third metal bump at a top of the first integrated-circuit (IC) chip and having a copper layer with a thickness between 2 and 20 micrometers, wherein the second metal bump is bonded to the third metal bump.
8 . The chip package of claim 7 , wherein the third metal bump further comprises a second tin-containing cap over the copper layer and bonded to the first tin-containing cap of the second metal bump.
9 . The chip package of claim 1 , wherein the first integrated-circuit (IC) chip comprises a silicon substrate, a transistor at a top of the silicon substrate and a third interconnection scheme over the silicon substrate.
10 . The chip package of claim 1 , wherein the first integrated-circuit (IC) chip comprises a silicon substrate and a through silicon via (TSV) vertically in the silicon substrate.
11 . The chip package of claim 1 , wherein the first integrated-circuit (IC) chip is a memory chip.
12 . The chip package of claim 1 , wherein the first integrated-circuit (IC) chip is a dynamic-random-access-memory (DRAM) chip.
13 . The chip package of claim 1 , wherein the first integrated-circuit (IC) chip is a logic chip.
14 . The chip package of claim 1 , wherein the second integrated-circuit (IC) chip is a logic chip.
15 . The chip package of claim 1 , wherein the optical chip further comprises an optical modulator under the insulating layer and having a portion in the silicon layer, wherein the optical modulator is configured to transmit a second optical signal to the optical fiber.
16 . The chip package of claim 1 , wherein the optical chip further comprises a photodetector under the insulating layer, wherein the photodetector is configured to be coupled to the optical fiber by the first optical signal.
17 . The chip package of claim 1 , wherein the optical chip further comprises an optical grating coupler under the insulating layer and having a portion in the silicon layer, wherein the optical grating coupler is configured to be coupled to the optical fiber by the first optical signal.
18 . The chip package of claim 1 , wherein the insulating layer of the optical chip comprises silicon oxide.
19 . The chip package of claim 1 , wherein the sub-system package further comprises a first sealing layer over the first interconnection scheme and at a same horizontal level as the first integrated-circuit (IC) chip.
20 . The chip package of claim 19 , wherein the first sealing layer comprises a molding compound.
21 . The chip package of claim 19 , wherein the second integrated-circuit (IC) chip is further over the first sealing layer and across an edge of the first integrated-circuit (IC) chip.
22 . The chip package of claim 19 further comprising a second sealing layer over the circuit substrate and at a same horizontal level as the sub-system package.
23 . The chip package of claim 22 , wherein the second sealing layer comprises a molding compound.
24 . The chip package of claim 1 , wherein the first integrated-circuit (IC) chip is an input/output (I/O) chip and the second integrated-circuit (IC) chip is a logic chip.
25 . The chip package of claim 1 , wherein the first integrated-circuit (IC) chip is an input/output (I/O) chip and the second integrated-circuit (IC) chip is a graphic-processing-unit (GPU) integrated-circuit (IC) chip.
26 . The chip package of claim 1 , wherein the circuit substrate comprises a plurality of metal pads at a top of the circuit substrate, wherein the first metal bump at the bottom of the sub-system package is bonded to one of the plurality of metal pads and each of the plurality of second solder balls at the bottom of the optical module couples to one of the plurality of metal pads.
27 . The chip package of claim 1 , wherein the optical module couples to the sub-system package through the circuit substrate.
28 . The chip package of claim 1 , wherein the optical module is further over the first interconnection scheme of the sub-system package.