Integrated devices in semiconductor packages and methods of forming same

1. A method of manufacturing a package structure, the method comprising:

encapsulating an integrated circuit die in an encapsulant external to the integrated circuit die;

forming a conductive via in the encapsulant and electrically connecting the integrated circuit die to a patch antenna, wherein the patch antenna comprises:

a ground element;

a feed line; and

a radiating element electrically coupled to the ground element and the feed line; and

forming a dielectric feature physically separating the ground element from the integrated circuit die, wherein a thickness of the dielectric feature is selected in accordance with at least one of: an operating bandwidth of the patch antenna, a k-value of the dielectric feature, an area of the patch antenna, and an efficiency of the patch antenna.

2. The method of claim 1 , wherein the dielectric feature comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer comprises a different material than the second dielectric layer.

3. The method of claim 2 , wherein the dielectric feature further comprises a third dielectric layer comprising a different material than at least one of the first dielectric layer and the second dielectric layer.

4. The method of claim 1 , wherein sidewalls of the dielectric feature are co-terminus with sidewalls of the integrated circuit die.

5. The method of claim 1 , wherein the dielectric feature has a different width than the integrated circuit die.

6. The method of claim 1 further comprising forming a radiating antenna extending through the encapsulant and electrically connected to the integrated circuit die.

7. A method comprising:

forming a ground element and a feed line of a patch antenna over a carrier;

attaching an integrated circuit die to the ground element of the patch antenna using a dielectric feature, wherein a thickness of the dielectric feature is selected in accordance with an operating bandwidth of the patch antenna, a k-value of the dielectric feature, an area of the patch antenna, an efficiency of the patch antenna, or a combination thereof;

forming a plurality of conductive vias electrically connected to the ground element and the feed line;

encapsulating the integrated circuit die and the plurality of conductive vias in an encapsulant, wherein the encapsulant is external to the integrated circuit die;

electrically connecting the plurality of conductive vias to the integrated circuit die using a redistribution layer, wherein the redistribution layer is disposed on an opposing side of the integrated circuit die as the ground element; and

electrically coupling a radiating element of the patch antenna to the ground element and the feed line.

8. The method of claim 7 further comprising:

removing the carrier;

after removing the carrier, forming a dielectric layer over the ground element and the feed line; and

forming the radiating element over the dielectric layer.

9. The method of claim 8 , wherein forming the radiating element comprises adhering the radiating element to the dielectric layer.

10. The method of claim 7 further comprising:

while forming the plurality of conductive vias, forming a radiating antenna;

encapsulating the radiating antenna with the plurality of conductive vias and the integrated circuit die; and

electrically connecting the radiating antenna to the integrated circuit die using the redistribution layer.

11. The method of claim 7 , wherein forming the ground element and the feed line comprises forming the ground element and the feed line simultaneously.

12. The method of claim 7 , wherein forming the ground element and the feed line comprises forming the ground element and the feed line in different dielectric layers.

13. A method comprising:

electroplating a ground line and a signal line over a carrier;

attaching an integrated circuit die to the carrier using a dielectric feature, the ground line being disposed between the carrier and the integrated circuit die, wherein the ground line and the signal line are components of a device, and wherein a thickness of the dielectric feature is selected in accordance with an operating bandwidth of the device;

encapsulating the integrated circuit die in a molding compound, wherein the molding compound is external to the integrated circuit die;

electrically connecting the integrated circuit die to the device using a conductive via in the molding compound; and

removing the carrier.

14. The method of claim 13 , wherein the thickness of the dielectric feature is further selected in accordance with a k-value of the dielectric feature, an area of the device, an efficiency of the device, or a combination thereof.

15. The method of claim 14 , wherein:

the thickness of the dielectric feature is at least 100 μm when the operating bandwidth of the device is 60 gHz and the k-value of the dielectric feature is at least 3;

the thickness of the dielectric feature is at least 30 μm when the operating bandwidth of the device is 60 gHz and the k-value of the dielectric feature is less than 3;

the thickness of the dielectric feature is at least 50 μm when the operating bandwidth of the device is 77 gHz and the k-value of the dielectric feature at least 3; and

the thickness of the dielectric feature is at least 15 μm when the operating bandwidth of the device is 77 gHz and the k-value of the dielectric feature is less than 3.

16. The method of claim 13 , wherein the device is a patch antenna, and wherein the method further comprises after removing the carrier, attaching a radiating element to an opposing side of the ground line as the integrated circuit die.

17. The method of claim 13 , wherein attaching an integrated circuit die to the carrier using a dielectric feature comprises disposing a portion of the dielectric feature in an opening between the ground line and the signal line.

18. The method of claim 17 , wherein the opening encircles the signal line in a top down view.

19. The method of claim 13 , wherein electroplating a ground line and a signal line over a carrier comprises electroplating the ground line after electroplating the signal line.

20. The method of claim 13 , wherein the device is a coplanar wave guide, and wherein the signal line is disposed between the ground element and an additional ground element in a top down view.