Molded chip combination
Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.
1. A molded chip combination, comprising:
a first semiconductor chip having a first PHY region;
a second semiconductor chip having a second PHY region;
an interconnect chip interconnecting the first PHY region to the second PHY region;
a first molding layer laterally joining together the first semiconductor chip and the second semiconductor chip;
a second molding layer at least partially encapsulating the interconnect chip; and
a polymer layer positioned between the first molding layer and the second molding layer.
2. The molded chip combination of claim 1 , wherein the first semiconductor chip includes a first plurality of interconnects to connect to a circuit board when the molded chip combination is mounted on the circuit board and the second semiconductor chip includes a second plurality of interconnects to connect to the circuit board when the molded chip combination is mounted on the circuit board.
3. The molded chip combination of claim 2 , wherein the first semiconductor chip includes a first non-PHY region connected to the first interconnects and the second semiconductor chip includes a second non-PHY region connected to the second interconnects.
4. The molded chip combination of claim 1 , wherein the first semiconductor chip includes a first non-PHY region, the first semiconductor chip PHY region having a first group of conductor pads each having a first lateral dimension and the first semiconductor chip non-PHY region has a second group of conductor pads each having substantially the same first lateral dimension, the polymer layer having a plurality of openings aligned with the first group of conductor pads and a plurality of interconnected openings aligned with the second group of conductor pads, the polymer layer having a conductive pillar in each of the openings and interconnected conductive pillars in each of the interconnected openings.
5. The molded chip combination of claim 4 , comprising another conductive pillar on the interconnected conductive pillars, the another conductive pillar having second lateral dimension larger than the first lateral dimension.
6. The molded chip combination of claim 1 , comprising a circuit board and the molded chip combination mounted on the circuit board.
7. The molded chip combination of claim 1 , wherein the first semiconductor chip comprises a processor and the second semiconductor chip comprises a memory chip.
8. A molded chip combination, comprising:
a first semiconductor chip having a first PHY region and a first non-PHY region;
a second semiconductor chip having a second PHY region and a second non-PHY region;
an interconnect chip interconnecting the first PHY region to the second PHY region;
a first molding layer laterally joining together the first semiconductor chip and the second semiconductor chip;
a second molding layer joined to the first molding layer and at least partially encapsulating the interconnect chip and the first molding layer; and
a polymer layer positioned between the first molding layer and the second molding layer.
9. The molded chip combination of claim 8 , wherein the first semiconductor chip includes a first plurality of interconnects to connect to a circuit board when the molded chip combination is mounted on the circuit board and the second semiconductor chip includes a second plurality of interconnects to connect to the circuit board when the molded chip combination is mounted on the circuit board.
10. The molded chip combination of claim 9 , wherein the first semiconductor chip first non-PHY region is connected to the first interconnects and the second semiconductor chip second non-PHY region is connected to the second interconnects.
11. The molded chip combination of claim 8 , wherein the first semiconductor chip PHY region includes a first group of conductor pads each having a first lateral dimension and the first semiconductor chip non-PHY region includes a second group of conductor pads each having substantially the same first lateral dimension, the polymer layer having a plurality of openings aligned with the first group of conductor pads and a plurality of interconnected openings aligned with the second group of conductor pads, the polymer layer having a conductive pillar in each of the openings and interconnected conductive pillars in each of the interconnected openings, the first semiconductor chip non-PHY region including another conductive pillar on the interconnected conductive pillars, the another conductive pillar having second lateral dimension larger than the first lateral dimension.
12. The molded chip combination of claim 8 , comprising a circuit board and the molded chip combination mounted on the circuit board.
13. The molded chip combination of claim 8 , wherein the first semiconductor chip comprises a processor and the second semiconductor chip comprises a memory chip.
14. A method of manufacturing a molded chip combination, comprising:
interconnecting a first PHY region of a first semiconductor chip to a second PHY region of a second semiconductor chip with an interconnect chip; and
molding together the first semiconductor chip and the second semiconductor chip with a first molding layer;
at least partially encapsulating the interconnect chip with a second molding layer; and
applying a polymer layer between the first molding layer and the second molding layer.
15. The method of claim 14 , comprising fabricating a first plurality of interconnects on the first semiconductor chip to connect to a circuit board when the molded chip combination is mounted on the circuit board and a second plurality of interconnects on the second semiconductor chip to connect to the circuit board when the molded chip combination is mounted on the circuit board.
16. The method of claim 15 , wherein the first semiconductor chip includes a first non-PHY region connected to the first interconnects and the second semiconductor chip includes a second non-PHY region connected to the second interconnects.
17. The method of claim 14 , wherein the first semiconductor chip includes a first non-PHY region, the method comprises fabricating a first group of conductor pads of the first semiconductor chip PHY region each having a first lateral dimension and a second group of conductor pads of the first semiconductor chip non-PHY region each having substantially the same first lateral dimension, providing the polymer layer with a plurality of openings aligned with the first group of conductor pads and a plurality of interconnected openings aligned with the second group of conductor pads, and fabricating a conductive pillar in each of the openings and interconnected conductive pillars in each of the interconnected openings.
18. The method of claim 17 , comprising positioning another conductive pillar on the interconnected conductive pillars, the another conductive pillar having second lateral dimension larger than the first lateral dimension.
19. The method of claim 14 , comprising mounting the molded chip combination on a circuit board.
20. The method of claim 14 , wherein the first semiconductor chip comprises a processor and the second semiconductor chip comprises a memory chip.