Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.
1 . A chip package comprising:
an element comprising a first silicon substrate, a first through silicon via vertically in the first silicon substrate, wherein the first through silicon via comprises a first copper layer vertically in the first silicon substrate and a first adhesion metal layer at a sidewall of the first copper layer, a first silicon-oxide-containing layer over the first silicon substrate, and a first bonding pad in a first opening in the first silicon-oxide-containing layer and coupling to the through silicon via, wherein the first bonding pad comprises a second copper layer in the first opening in the first silicon-oxide-containing layer and a second adhesion metal layer having a first portion at a sidewall of the second copper layer and a second portion at a bottom of the second copper layer;
a first semiconductor chip over and bonded to the element, wherein the first semiconductor chip comprises a second silicon substrate, a transistor at a bottom of the second silicon substrate, a first interconnection metal layer under the second silicon substrate, a second silicon-oxide-containing layer under the second silicon substrate and first interconnection metal layer and a second bonding pad under and on the first interconnection metal layer and in a second opening in the second silicon-oxide-containing layer, wherein the first interconnection metal layer comprises a third copper layer and a third adhesion metal layer having a first portion at a sidewall of the third copper layer and a second portion at a top of the third copper layer, and wherein the second bonding pad comprises a fourth copper layer in the second opening in the second silicon-oxide-containing layer and a fourth adhesion metal layer having a first portion at a sidewall of the fourth copper layer and a second portion at a top of the fourth copper layer, between the fourth copper layer and first interconnection metal layer and in contact with the first interconnection metal layer, wherein the fourth copper layer has a bottom surface bonded to and in contact with a top surface of the second copper layer and the second silicon-oxide-containing layer has a bottom surface bonded to and in contact with a top surface of the first silicon-oxide-containing layer, wherein the element couples to the first semiconductor chip through the first and second bonding pads; and
a sealing layer over the element and at a same horizontal level as the first semiconductor chip.
2 . The chip package of claim 1 , wherein the first bonding pad is vertically over the first through silicon via.
3 . The chip package of claim 1 further comprising a metal contact at a bottom of the element.
4 . The chip package of claim 3 , wherein the metal contact is a metal bump.
5 . The chip package of claim 3 , wherein the metal contact comprises a fifth copper layer having a thickness between 1 and 50 micrometers.
6 . The chip package of claim 4 , wherein the metal bump comprises a fifth copper layer and a tin-containing layer under the fifth copper layer.
7 . The chip package of claim 3 , wherein the metal contact is vertically under and aligned with the first through silicon via.
8 . The chip package of claim 1 , wherein the first silicon-oxide-containing layer has a thickness between 0.1 and 2 micrometers and contacts a sidewall of the first bonding pad.
9 . The chip package of claim 1 , wherein the second silicon-oxide-containing layer has a thickness between 0.1 and 2 micrometers and contacts a sidewall of the second bonding pad.
10 . The chip package of claim 1 further comprising a second semiconductor chip over and bonded to the element.
11 . The chip package of claim 10 , wherein the second semiconductor chip comprises a third silicon substrate and a third silicon-oxide-containing layer under the third silicon substrate, wherein the third silicon-oxide-containing layer has a bottom surface bonded to and in contact with the top surface of the first silicon-oxide-containing layer.
12 . The chip package of claim 11 , wherein the second semiconductor chip further comprises a third bonding pad under the third silicon substrate and in a third opening in the third silicon-oxide-containing layer, wherein the third bonding pad comprises a fifth copper layer in the third opening in the third silicon-oxide-containing layer and a fifth adhesion metal layer having a first portion at a sidewall of the fifth copper layer and a second portion at a top of the fifth copper layer.
13 . The chip package of claim 12 , wherein the first semiconductor chip is a logic chip and the second semiconductor chip is a memory chip.
14 . The chip package of claim 1 , wherein the first semiconductor chip is a logic chip.
15 . The chip package of claim 1 , wherein the first semiconductor chip is a memory chip.
16 . The chip package of claim 1 , wherein the first semiconductor chip is a statistic-random-access memory (SRAM) chip.
17 . The chip package of claim 1 , wherein the first semiconductor chip is a dynamic-random-access memory (DRAM) chip.
18 . The chip package of claim 1 , wherein the sealing layer has a sidewall coplanar, in a vertical direction, with a sidewall of the element.
19 . The chip package of claim 1 , wherein the sealing layer comprises a portion extending, in a horizontal direction, beyond a sidewall of the first semiconductor chip to an edge of the element.
20 . The chip package of claim 1 , wherein the second adhesion metal layer comprises titanium.
21 . The chip package of claim 1 , wherein the fourth adhesion metal layer comprises titanium.
22 . The chip package of claim 1 , wherein the element further comprises an interconnection scheme over the first silicon substrate, wherein the first silicon-oxide-containing layer is over the interconnection scheme and the first bonding pad is over and couples to the interconnection scheme.
23 . The chip package of claim 22 , wherein the interconnection scheme comprises a second interconnection metal layer under the first bonding pad and first silicon-oxide-containing layer and in contact with the second portion of the second adhesion metal layer of the first bonding pad, wherein the second interconnection metal layer comprises a fifth copper layer and a fifth adhesion metal layer having a first portion at a sidewall of the fifth copper layer and a second portion at a bottom of the fifth copper layer.
24 . The chip package of claim 23 , wherein the element further comprises a second through silicon via vertically in the first silicon substrate and the interconnection scheme further comprises a third interconnection metal layer under the second interconnection metal layer and a first insulating dielectric layer between the second and third interconnection metal layers, wherein the third interconnection metal layer comprises a sixth copper layer and a sixth adhesion metal layer having a first portion at a sidewall of the sixth copper layer and a second portion at a bottom of the sixth copper layer, wherein the third interconnection metal layer is in contact with a top of the second through silicon via.
25 . The chip package of claim 24 , wherein the second through silicon via comprises a seventh copper layer and a seventh adhesion metal layer at a sidewall of the seventh copper layer, wherein the third interconnection metal layer is in contact with a top surface of the seventh copper layer of the second through silicon via at the top of the second through silicon via.
26 . The chip package of claim 24 , wherein the interconnection scheme further comprises a second insulating dielectric layer under a first portion of the third interconnection metal layer, wherein the third interconnection metal layer has a second portion in an opening in the second insulating dielectric layer and in contact with the top of the second through silicon via.