Redistribution structures for semiconductor packages and methods of forming the same

1. A method comprising:

encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector;

depositing a non-planar first dielectric layer over the molding compound;

patterning a first opening through the non-planar first dielectric layer exposing the die connector of the integrated circuit die, wherein the patterning the first opening comprises exposing a top surface of the non-planar first dielectric layer to a patterned energy source using a proximity aligner, wherein a proximity photomask is separated from the top surface of the non-planar first dielectric layer while exposing the top surface of the non-planar first dielectric layer to the patterned energy source;

after patterning the first opening through the non-planar first dielectric layer, planarizing the non-planar first dielectric layer such that the first dielectric layer comprises a planar top surface;

depositing a first seed layer over the planar top surface of the first dielectric layer and in the first opening; and

plating a first conductive via extending through the planar top surface of the first dielectric layer on the first seed layer.

2. The method of claim 1 , wherein the planarizing the non-planar first dielectric layer comprises a chemical mechanical planarization (CMP) process.

3. The method of claim 1 , wherein an entirety of the top surface of the non-planar first dielectric layer is exposed to the patterned energy source simultaneously.

4. The method of claim 1 , further comprising depositing a photoresist over the first seed layer and exposing the photoresist to a second patterned energy source using an aligner.

5. The method of claim 4 , wherein an entire top surface of the photoresist is exposed to the second patterned energy source simultaneously.

6. The method of claim 1 , further comprising:

depositing a second dielectric layer over the planar top surface of the first dielectric layer and the first conductive via;

patterning a second opening through the second dielectric layer exposing the first conductive via;

planarizing the second dielectric layer;

depositing a second seed layer over the second dielectric layer and in the second opening; and

plating a second conductive via extending through the second dielectric layer on the second seed layer.

7. The method of claim 1 , wherein the proximity photomask is separated from the top surface of the non-planar first dielectric layer by a gap ranging from about 10 mm to about 150 mm, and wherein the gap is filled with nitrogen.

8. A method comprising:

encapsulating a plurality of integrated circuit dies in a molding compound, each one of the plurality of integrated circuit dies being disposed on a wafer, each one of the plurality of integrated circuit dies having a die connector;

depositing a first dielectric layer over the molding compound and the plurality of integrated circuit dies, wherein the first dielectric layer is deposited with a non-planar top surface;

simultaneously exposing an entirety of an upper surface of the first dielectric layer to a first patterned energy source using a contact aligner, wherein exposing the first dielectric layer to the first patterned energy comprises bringing a contact photomask into direct contact with the upper surface of the first dielectric layer;

developing the first dielectric layer to form a first plurality of openings exposing the plurality of integrated circuit dies;

planarizing the first dielectric layer; and

forming a first metallization pattern through the first dielectric layer, the first metallization pattern contacting the die connectors.

9. The method of claim 8 , wherein the forming the first metallization pattern comprises:

forming a seed layer over the first dielectric layer;

forming a photoresist over the seed layer;

simultaneously exposing an entire upper surface of the photoresist to a second patterned energy source;

developing the photoresist to form a second plurality of openings exposing the seed layer; and

plating a conductive material in the second plurality of openings.

10. The method of claim 8 , further comprising:

depositing a second dielectric layer over the first dielectric layer and the first metallization pattern;

simultaneously exposing an entire upper surface of the second dielectric layer to a second patterned energy source;

developing the second dielectric layer to form a second plurality of openings exposing the first metallization pattern;

planarizing the second dielectric layer; and

forming a second metallization pattern through the second dielectric layer, the second metallization pattern contacting the first metallization pattern, wherein the second metallization pattern has an overlay shift of less than 2 μm with respect to the first metallization pattern.

11. The method of claim 8 , wherein the first dielectric layer is planarized after the developing the first dielectric layer.

12. The method of claim 8 , wherein the entire upper surface of the first dielectric layer is exposed by projecting an energy source through a mask, wherein the mask produces the first patterned energy source.

13. The method of claim 12 , wherein the mask has a diameter substantially identical to a diameter of the wafer.

14. The method of claim 8 , wherein the first dielectric layer is planarized before the simultaneously exposing the entire upper surface of the first dielectric layer.

15. A method comprising:

encapsulating an integrated circuit die and a through via adjacent the integrated circuit die with a molding compound; and

forming a redistribution structure over the integrated circuit die, the molding compound, and the through via, wherein forming the redistribution structure comprises:

depositing a first dielectric layer having a non-planar surface over the integrated circuit die, the through via, and the molding compound;

patterning the first dielectric layer to form first openings extending through the first dielectric layer, the first openings exposing surfaces of the through via and the integrated circuit die, wherein patterning the first dielectric layer comprises exposing an upper surface of the first dielectric layer to a first patterned energy source using a proximity aligner, wherein a proximity photomask is separated from the upper surface of the first dielectric layer while exposing the upper surface of the first dielectric layer to the first patterned energy source;

after the patterning the first dielectric layer, planarizing the first dielectric layer; and

depositing first conductive features in the first openings, the first conductive features being electrically connected to the integrated circuit die and the through via.

16. The method of claim 15 , wherein the patterning the first dielectric layer comprises exposing an entire upper surface of the first dielectric layer to a patterned energy source.

17. The method of claim 16 , wherein an aligner is used to expose the entire upper surface of the first dielectric layer to the patterned energy source.

18. The method of claim 15 , further comprising:

depositing a second dielectric layer over the first dielectric layer and the first conductive features;

patterning the second dielectric layer to form second openings extending through the second dielectric layer, the second openings exposing surfaces of the first conductive features;

after the patterning the second dielectric layer, planarizing the second dielectric layer; and

depositing second conductive features in the second openings, the second conductive features being electrically connected to the first conductive features.

19. The method of claim 15 , wherein the first dielectric layer is planarized to a degree of planarization greater than 95 percent.

20. The method of claim 15 , wherein the first openings are patterned with a pitch of equal to or less than 2 μm.