Method of integrating a charge-trapping gate stack into a CMOS flow
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
1. An apparatus comprising:
a substrate having a surface;
a dielectric stack formed on the surface in a first region, the dielectric stack comprising:
a tunneling dielectric formed directly on the surface of the substrate, and
a charge-trapping layer formed directly on the tunneling dielectric;
a blocking oxide formed overlying the charge-trapping layer; and
a gate oxide of a field-effect transistor (FET) formed on the surface in a second region, the gate oxide formed simultaneous to the blocking oxide.
2. The apparatus of claim 1 , wherein the blocking oxide and the gate oxide have substantially the same thermal quality.
3. The apparatus of claim 2 , wherein at least a portion of the blocking oxide is formed by consuming at least a portion of the charge-trapping layer.
4. The apparatus of claim 2 , wherein an oxidation consumes substantially no portion of the charge-trapping layer.
5. The apparatus of claim 2 , wherein the charge-trapping layer comprises a first layer and a second layer, the first layer between the second layer and the tunneling dielectric, and wherein the second layer comprises a greater number of charge traps than the first layer.
6. The apparatus of claim 5 , wherein the first layer includes silicon nitride, silicon-rich silicon nitride, or silicon oxy-nitride.
7. The apparatus of claim 5 , wherein the second layer includes a silicon nitride or a silicon oxy-nitride and wherein the second layer has a stoichiometric composition substantially different from the first layer.
8. The apparatus of claim 5 , wherein a middle oxide layer is disposed between the first layer and the second layer.
9. A non-volatile memory device comprising:
a substrate having a surface;
a dielectric stack formed on the surface in a first region, the dielectric stack comprising:
a tunneling dielectric formed directly on the surface of the substrate, and
a charge-trapping layer formed directly on the tunneling dielectric;
a blocking layer formed overlying the charge-trapping layer;
a first gate layer formed overlying the blocking layer;
a first gate oxide layer of a metal-oxide-semiconductor (MOS) device formed on the surface in a second region, the first gate oxide layer formed simultaneous with the blocking layer;
a second gate oxide layer of the MOS device formed on the surface in the second region;
a second gate layer formed on the first gate oxide layer; and
a third gate layer formed on the second gate oxide layer, wherein the first, second, and third gate layers are formed substantially simultaneously.
10. The non-volatile memory device of claim 9 , wherein the second gate layer comprises a metal-containing material.
11. The non-volatile memory device of claim 10 , wherein the metal-containing material includes one of a group comprising: metal nitrides, metal carbides, metal silicide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt and nickel.
12. The non-volatile memory device of claim 9 , wherein the first gate layer comprises a doped poly-crystalline silicon.
13. The non-volatile memory device of claim 9 , wherein the first gate layer is formed on a channel disposed on the substrate.
14. The non-volatile memory device of claim 9 , wherein the first gate oxide layer is formed on a pad oxide layer formed on or over the substrate.
15. A semiconductor device comprising:
a substrate having a surface;
a dielectric stack formed on the surface in a first region, the dielectric stack comprising:
a tunneling dielectric formed directly on the surface of the substrate, and
a charge-trapping layer formed directly on the tunneling dielectric;
a blocking oxide formed overlying the charge-trapping layer;
a MOS device disposed on the substrate, the MOS device comprising:
a first gate oxide formed on the substrate, the first gate oxide formed simultaneous to the blocking oxide,
a first gate formed on the first gate oxide, and
a first plurality of spacers formed adjacent to the first gate; and
an HV MOS device, the HV MOS device comprising:
a second gate oxide formed on the substrate,
a second gate formed on the second gate oxide, and
a second plurality of spacers formed adjacent to the second gate.
16. The semiconductor device of claim 15 , further comprising extension regions within the substrate, the extension regions substantially below the MOS device or the HV MOS device.
17. The semiconductor device of claim 15 , further comprising at least one drain region within the substrate.
18. The semiconductor device of claim 15 , wherein the first gate comprises a metal-containing material.
19. The semiconductor device of claim 18 , wherein the metal-containing material includes one of a group comprising: metal nitrides, metal carbides, metal silicide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt and nickel.
20. The semiconductor device of claim 15 , wherein the first gate comprises a doped poly-crystalline silicon.