Multi-output look-up table (LUT) for use in coarse-grained field-programmable-gate-array (FPGA) integrated-circuit (IC) chip
A semiconductor integrated-circuit (IC) chip comprises a memory cell including: a latch circuit comprising first and second inverters coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter; a first N-type MOS transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first output point of the memory cell, and a first gate terminal for controlling coupling between the first latch node and the first output point of the memory cell; a second N-type MOS transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second output point of the memory cell, and a second gate terminal for controlling coupling between the second latch node and the second output point of the memory cell; and a P-type MOS transistor having a fifth terminal coupling to the first latch node, a sixth terminal coupling to a third output point of the memory cell, and a third gate terminal for controlling coupling between the first latch node and the third output point of the memory cell.
1 . A semiconductor integrated-circuit (IC) chip comprising:
a memory array comprising:
a plurality of first bit lines,
a plurality of bit-bar lines,
a plurality of second bit lines,
a plurality of first word lines,
a plurality of second word lines, and
a plurality of dual-port memory cells arranged in an array of multiple columns by multiple rows, wherein each of the plurality of dual-port memory cells comprises:
a six-transistor (6T) static-random-access memory (SRAM) cell comprising a first and a second transfer transistor each having a gate terminal coupling to a first word line of the plurality of first word lines, a first latch node coupling to a first bit line of the plurality of first bit lines through the first transfer transistor and a second latch node coupling to a bit-bar line of the plurality of bit-bar lines through the second transfer transistor, and
a third transfer transistor having a gate terminal coupling to a second word line of the plurality of second word lines, wherein the third transfer transistor is coupled between the first latch node and a second bit line of the plurality of second bit lines;
a first row decoder coupling to the plurality of first word lines, wherein the first row decoder is configured for switching on the first and second transfer transistors of the six-transistor (6T) static-random-access memory (SRAM) cell of said each of the plurality of dual-port memory cells arranged in one of the multiple rows of the array in accordance with first data at the first word line; and
a first column decoder coupling to the plurality of first bit lines and the plurality of bit-bar lines, wherein the first column decoder is configured for writing second data into said each of the plurality of dual-port memory cells to be stored therein through the first bit line and bit-bar line.
2 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein each of the first and second transfer transistors is an N-type metal-oxide-semiconductor (MOS) transistor.
3 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the third transfer transistor is a P-type metal-oxide-semiconductor (MOS) transistor.
4 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the third transfer transistor is a fin field-effect transistor (finFET).
5 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the third transfer transistor is a gate-all-around (GAA) field-effect transistor (FET).
6 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein a voltage of power supply applied to the six-transistor (6T) static-random-access memory (SRAM) cell is less than 0.5 volts.
7 . The semiconductor integrated-circuit (IC) chip of claim 1 further comprising:
a second row decoder coupling to the plurality of second word lines, wherein the second row decoder is configured for switching on the third transfer transistor of said each of the plurality of dual-port memory cells arranged in said one of the multiple rows of the array in accordance with third data at the second word line; and
a second column decoder coupling to the plurality of second bit lines, wherein the second column decoder is configured for reading the second data stored in said each of the plurality of dual-port memory cells through the second bit line as output data of the second column decoder.
8 . The semiconductor integrated-circuit (IC) chip of claim 7 further comprising a selection circuit having first address data having k bits at its input points, wherein the first address data comprises row-address data having r bits and column-address data having c bits, wherein k, r and c are positive integers, wherein the selection circuit is configured for selecting the row-address data from the first address data as first output data to be passed to the second row decoder, and the second row decoder is configured for selecting, in accordance with the row-address data, the second word line from the plurality of second word lines to pass the third data at the second word line, and wherein the selection circuit is configured for selecting the column-address data from the first address data as second output data to be passed to the second column decoder, and the second column decoder is configured for selecting, in accordance with the column-address data, the second bit line from the plurality of second bit lines to read the second data stored in said each of the plurality of dual-port memory cells.
9 . The semiconductor integrated-circuit (IC) chip of claim 7 further comprising a registering block configured for storing data associated with the output data of the second column decoder.
10 . The semiconductor integrated-circuit (IC) chip of claim 7 , wherein the second row decoder, second column decoder and memory array are configured for a multi-output look-up table (LUT).
11 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the first column decoder is further configured for reading the second data stored in said each of the plurality of dual-port memory cells through the first bit line and bit-bar line.
12 . The semiconductor integrated-circuit (IC) chip of claim 1 further comprising a sense amplifier coupling to the first bit line and bit-bar line to sense a first voltage at the first bit line and a second voltage at the bit-bar line and amplify a difference between the first and second voltages as a data output of the sense amplifier.
13 . The semiconductor integrated-circuit (IC) chip of claim 1 , wherein the six-transistor (6T) static-random-access memory (SRAM) cell comprises a latch circuit having a first and a second inverter coupling to each other, wherein the first latch node couples to an input point of the first inverter and an output point of the second inverter and the second latch node couples to an input point of the second inverter and an output point of the first inverter.
14 . The semiconductor integrated-circuit (IC) chip of claim 1 is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
15 . The semiconductor integrated-circuit (IC) chip of claim 1 is an application specific integrated-circuit (ASIC) chip.
16 . The semiconductor integrated-circuit (IC) chip of claim 1 is a central processing unit (CPU) integrated-circuit (IC) chip.
17 . A semiconductor integrated-circuit (IC) chip comprising:
a memory array comprising:
a plurality of first bit lines,
a plurality of bit-bar lines,
a plurality of second bit lines,
a plurality of first word lines,
a plurality of second word lines, and
a plurality of memory cells arranged in an array of multiple columns by multiple rows, wherein each of the plurality of memory cells comprises:
a latch circuit comprising a first and a second inverter coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter,
a first N-type metal-oxide-semiconductor (MOS) transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first point of said each of the plurality of memory cells, and a first gate terminal coupling to a first word line of the plurality of first word lines, wherein the first N-type metal-oxide-semiconductor (MOS) transistor is configured for controlling coupling between the first latch node and the first point of said each of the plurality of memory cells,
a second N-type metal-oxide-semiconductor (MOS) transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second point of said each of the plurality of memory cells, and a second gate terminal coupling to the first word line, wherein the second N-type metal-oxide-semiconductor (MOS) transistor is configured for controlling coupling between the second latch node and the second point of said each of the plurality of memory cells, wherein a first voltage level at the first point of said each of the plurality of memory cells is reversed to a second voltage level at the second point of said each of the plurality of memory cells, and
a P-type metal-oxide-semiconductor (MOS) transistor having a fifth terminal coupling to the first latch node, a sixth terminal coupling to a third point of said each of the plurality of memory cells, and a third gate terminal coupling to a second word line of the plurality of second word lines, wherein the P-type metal-oxide-semiconductor (MOS) transistor is configured for controlling coupling between the first latch node and the third point of said each of the plurality of memory cells, wherein a third voltage level at the third point of said each of the plurality of memory cells is the same as the first voltage level;
a first row decoder coupling to the plurality of first word lines, wherein the first row decoder is configured for switching on the first and second N-type metal-oxide-semiconductor (MOS) transistors of said each of the plurality of memory cells arranged in one of the multiple rows of the array in accordance with first data at the first word line; and
a first column decoder coupling to the plurality of first bit lines and the plurality of bit-bar lines, wherein the first column decoder is configured for writing second data into said each of the plurality of memory cells to be stored therein through the first bit line and bit-bar line.
18 . The semiconductor integrated-circuit (IC) chip of claim 17 , wherein the P-type metal-oxide-semiconductor (MOS) transistor is a fin field-effect transistor (finFET).
19 . The semiconductor integrated-circuit (IC) chip of claim 17 , wherein the P-type metal-oxide-semiconductor (MOS) transistor is a gate-all-around (GAA) field-effect transistor (FET).
20 . The semiconductor integrated-circuit (IC) chip of claim 17 , wherein a voltage of power supply applied to said each of the plurality of memory cells is less than 0.5 volts.
21 . The semiconductor integrated-circuit (IC) chip of claim 17 is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.