Transistors with back-side contacts to create three dimensional memory and logic
Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.
1. An integrated circuit (IC) device, comprising:
a transistor that includes a channel material, a first source or drain (S/D) region, and a second S/D region;
a contact to the first S/D region; and
a contact to the second S/D region,
wherein:
the contact to the first S/D region is in a first layer,
the contact to the second S/D region is in a second layer,
a portion of the channel material between the first S/D region and the second S/D region is in a third layer,
the third layer is between the first layer and the second layer,
the contact to the second S/D region includes a capacitor that includes a first capacitor electrode, a second capacitor electrode, and an insulator between the first capacitor electrode and the second capacitor electrode,
the contact to the second S/D region further includes a first contact to the first capacitor electrode, and a second contact between the second S/D region and the second capacitor electrode, and
the IC device further includes a plateline, coupled to or including the first contact to the first capacitor electrode, and further coupled to a plate voltage generator.
2. The IC device according to claim 1 , further including:
a wordline, coupled to or including the contact to the gate stack, and
a bitline, coupled to or including the contact to the first S/D region.
3. The IC device according to claim 1 , wherein the capacitor is a metal-insulator-metal capacitor.
4. The IC device according to claim 1 , wherein at least a portion of the channel material is shaped as one of a fin, a nanowire, and a nanoribbon.
5. The IC device according to claim 1 , wherein the IC device is a memory device.
6. The IC device according to claim 1 , wherein:
the IC device is an IC package that includes an IC die and a further component, the further component coupled to the IC die, and
the IC die includes the transistor, the contact to the first S/D region, the contact to the second S/D region, and the plateline.
7. The IC device according to claim 1 , wherein:
the transistor further includes a gate stack over at least a portion of the channel material between the first S/D region and the second S/D region, and
the IC device further includes a contact to the gate stack.
8. The IC device according to claim 7 , wherein at least a portion of the contact to the gate stack is in the first layer.
9. The IC device according to claim 7 , wherein the gate stack includes a gate electrode material and a gate dielectric material, wherein the gate dielectric material is between the gate electrode material and the channel material.
10. An integrated circuit (IC) device, comprising:
a transistor, comprising a first source or drain (S/D) region and a second S/D region;
a capacitor, comprising a first capacitor electrode and a second capacitor electrode;
a contact to the first capacitor electrode;
a first conductive via structure; and
a second conductive via structure,
wherein:
the first conductive via structure is in conductive contact with the first S/D region,
the second conductive via structure is in conductive contact with the second S/D region, and
the second conductive via structure includes a first portion and a second portion, such that a portion of the second S/D region is between the first portion and the capacitor, and the second portion extends along a side of the second S/D region and is in conductive contact with the second capacitor electrode.
11. The IC device according to claim 10 , wherein the second portion is in conductive contact with the side of the second S/D region and is electrically continuous with the first portion.
12. The IC device according to claim 10 , wherein a dimension of the second portion in a direction that is substantially parallel to the support structure is smaller than a dimension of the first portion in the direction.
13. The IC device according to claim 10 , wherein the contact to the first capacitor electrode is coupled to a plate voltage generator.
14. The IC device according to claim 10 , wherein the IC device is a memory device.
15. The IC device according to claim 10 , wherein the first portion is in conductive contact with a top of the second S/D region.
16. The IC device according to claim 15 , wherein:
the IC device further includes a support structure,
the transistor is over the support structure,
the top of the second S/D region is a first face of the S/D region that is substantially parallel to the support structure and is further away from the support structure than a bottom of the second S/D region,
the bottom of the second S/D region is a second face of the S/D region that is substantially parallel to the support structure, and
the side of the second S/D region is substantially perpendicular to the support structure and extends between the bottom of the second S/D region and the top of the second S/D region.
17. The IC device according to claim 10 , wherein:
the IC device is an IC package that includes an IC die and a further component, the further component coupled to the IC die, and
the IC die includes the transistor, the contact to the first S/D region, the contact to the second S/D region, and the plateline.
18. The IC device according to claim 17 , wherein the further component is one of a package substrate, a flexible substrate, or an interposer.
19. A method of fabricating an integrated circuit (IC) device, the method comprising:
providing a transistor, comprising a first source or drain (S/D) region and a second S/D region;
providing a capacitor, comprising a first capacitor electrode and a second capacitor electrode;
providing a contact to the first capacitor electrode;
providing a first conductive via structure; and
providing a second conductive via structure,
wherein:
the first conductive via structure is in conductive contact with the first S/D region,
the second conductive via structure is in conductive contact with the second S/D region,
the second conductive via structure includes a first portion and a second portion, such that a portion of the second S/D region is between the first portion and the capacitor, and the second portion extends along a side of the second S/D region and is in conductive contact with the second capacitor electrode,
the second portion is in conductive contact with the side of the second S/D region and is electrically continuous with the first portion, and
the first portion is in conductive contact with a top of the second S/D region.
20. The method according to claim 19 , wherein:
the transistor is over the support structure,
a top of the second S/D region is a first face of the S/D region that is substantially parallel to the support structure and is further away from the support structure than a bottom of the second S/D region,
the bottom of the second S/D region is a second face of the S/D region that is substantially parallel to the support structure,
a side of the second S/D region is substantially perpendicular to the support structure and extends between the bottom of the second S/D region and the top of the second S/D region.