Three-dimensional folded static random-access memory
Described herein are SRAM cells in which some transistors are implemented as thin film transistors (TFTs) while other transistors are implemented as non-TFTs (e.g., as FinFETs or nanoribbon-based transistors), where the TFTs are folded over non-TFTs to realize high-density 3D SRAM. For a given SRAM cell, either N-type transistors may be implemented as TFTs and stacked above P-type transistors that are implemented as non-TFTs, or P-type transistors may be implemented as TFTs and may be stacked above N-type transistors that are implemented as non-TFTs.
1 . An integrated circuit (IC) device, comprising:
a base;
first and second semiconductor structures in a first layer over the base;
third and fourth semiconductor structures in a second layer over the base, wherein the second layer is either above the first layer or below the first layer; and
a memory cell comprising a plurality of transistors, wherein the plurality of transistors includes a transistor M 1 , a transistor M 2 , a transistor M 3 , a transistor M 4 , a transistor M 5 , and a transistor M 6 , wherein a channel portion of the transistor M 2 is a portion of the first semiconductor structure, a channel portion of the transistor M 4 is a portion of the second semiconductor structure, channel portions of the transistor M 1 and the transistor M 5 are different portions of the third semiconductor structure, and channel portions of the transistor M 6 and the transistor M 3 are different portions of the fourth semiconductor structure.
2 . The IC device according to claim 1 , wherein:
a projection of the third semiconductor structure onto the base at least partially overlaps with a projection of the first semiconductor structure onto the base, and
the IC device further includes a conductor extending between a region of the transistor M 6 and a region of the transistor M 4 ,
the region of the transistor M 6 is either a source region of the transistor M 6 or a drain region of the transistor M 6 , and
the region of the transistor M 4 is either a source region of the transistor M 4 or a drain region of the transistor M 4 .
3 . The IC device according to claim 2 , wherein the conductor is substantially perpendicular to the base.
4 . The IC device according to claim 2 , wherein a projection of a gate of the transistor M 3 onto the base is closer to a projection of a gate of the transistor M 4 onto the base than a projection of a gate of the transistor M 6 onto the base.
5 . The IC device according to claim 4 , wherein the conductor is a first conductor, and the IC device further includes a second conductor, wherein one portion of the first conductor is the gate of the transistor M 3 , and another portion of the conductor is the gate of the transistor M 4 .
6 . The IC device according to claim 5 , wherein the second conductor is substantially perpendicular to the base.
7 . The IC device according to claim 1 , wherein:
a region of the transistor M 6 is conductively coupled with a region of the transistor M 4 , a gate stack of the transistor M 1 , and a gate stack of the transistor M 2 ,
the region of the transistor M 6 is either a source region of the transistor M 6 or a drain region of the transistor M 6 , and
the region of the transistor M 4 is either a source region of the transistor M 4 or a drain region of the transistor M 4 .
8 . The IC device according to claim 1 , wherein the memory cell is a static random-access memory (SRAM) cell.
9 . An integrated circuit (IC) device, comprising:
a substrate;
first and second fins over the substrate;
a first structure stacked above the first fin and comprising a first thin film semiconductor;
a second structure stacked above the second fin and comprising a second thin film semiconductor; and
a static random-access memory (SRAM) cell comprising transistors M 1 , M 2 , M 3 , M 4 , M 5 , and M 6 , wherein channel portions of the transistors M 1 and M 5 are in different portions of the first structure, channel portions of the transistors M 6 and M 3 are in different portions of the second structure, a channel portion of the transistor M 2 is in a portion of the first fin, and a channel portion of the transistor M 4 is in a portion of the second fin.
10 . The IC device according to claim 9 , wherein:
each of the transistors M 1 and M 3 has first and second electrodes,
one of the first and second electrodes is a source electrode,
another one of the first and second electrodes is a drain electrode,
the first electrode of the transistor M 1 is closer to the substrate than the channel portion of the transistor M 1 ,
the second electrode of the transistor M 1 is further away from the substrate than the channel portion of the transistor M 1 ,
the first electrode of the transistor M 3 is closer to the substrate than the channel portion of the transistor M 3 , and
the second electrode of the transistor M 3 is further away from the substrate than the channel portion of the transistor M 3 .
11 . The IC device according to claim 9 , wherein each of the transistors M 1 and M 3 is a bottom-gated transistor.
12 . The IC device according to claim 9 , further comprising:
a conductive structure,
wherein a bottom end of the conductive structure is a gate electrode of the transistor M 2 , and a top end of the conductive structure is a gate electrode of the transistor M 1 .
13 . The IC device according to claim 12 , wherein the conductive structure is a first conductive structure, the IC device further includes a second conductive structure, a bottom end of the second conductive structure is a gate electrode of the transistor M 4 , and a top end of the conductive structure is a gate electrode of the transistor M 3 .
14 . The IC device according to claim 12 , wherein the conductive structure is a first conductive structure, the IC device further includes a second conductive structure, and a bottom end of the second conductive structure is a source electrode or a drain electrode of the transistor M 2 and a top end of the conductive structure is a source electrode or a drain electrode of the transistor M 1 .
15 . The IC device according to claim 12 , wherein the conductive structure is coupled to a region of the transistor M 3 and a region of the transistor M 4 , the region of the transistor M 3 is either a source region of the transistor M 3 or a drain region of the transistor M 3 , and the region of the transistor M 4 is either a source region of the transistor M 4 or a drain region of the transistor M 4 .
16 . The IC device according to claim 12 , wherein the conductive structure is substantially perpendicular to the substrate.
17 . The IC device according to claim 9 , wherein a pitch of the first fin and the second fin is between about 10 nanometers and 100 nanometers.
18 . The IC device according to claim 9 , wherein a width of the first structure is between about 10 nanometers and 100 nanometers, and a length of the first structure is larger than the width of the first structure.
19 . An integrated circuit (IC) device, comprising:
a die;
first and second layers over the die, wherein either the first layer is between the die and the second layer, or the second layer is between the die and the first layer; and
a memory cell comprising six transistors, wherein two transistors of the six transistors have channel portions in the first layer, four transistors of the six transistors have channel portions in the second layer, and the channel portion of a first transistor of the four transistors and the channel portion of a second transistor of the four transistors are different portions of a materially continuous semiconductor structure in the second layer.
20 . The IC device according to claim 19 , wherein the two transistors are transistors of a first type, and the four transistors are transistors of a second type, wherein one of the first type and the second type is an N-type and another one of the first type and the second type is a P-type.
21 . The IC device according to claim 19 , wherein:
a first region of the first transistor is coupled to, or shared with, a first region of the second transistor,
a second region of the first transistor is coupled to a reference voltage port and a second region of the second transistor is coupled to a bitline,
the first region of the first transistor is one of a source region or a drain region of the first transistor,
the second region of the first transistor is another one of the source region or the drain region of the first transistor,
the first region of the second transistor is one of a source region or a drain region of the second transistor, and
the second region of the second transistor is another one of the source region or the drain region of the second transistor.
22 . The IC device according to claim 21 , wherein:
the first region of the first transistor is coupled to a first region of one of the two transistors,
a second region of the one of the two transistors is coupled to an additional reference voltage,
the first region of the one of the two transistors is one of a source region or a drain region of the one of the two transistors,
the second region of the one of the two transistors is another one of the source region or the drain region of the one of the two transistors,
the channel portion of the one of the two transistors is a portion of a first semiconductor structure in the first layer, and
the channel portion of another one of the two transistors is a portion of a second semiconductor structure in the first layer.
23 . The IC device according to claim 22 , wherein a projection of the materially continuous semiconductor structure in the second layer onto the die at least partially overlaps with a projection of the first semiconductor structure onto the die.
24 . The IC device according to claim 19 , wherein the memory cell is a static random-access memory (SRAM) cell.