Released fin for advanced integrated circuit structure fabrication
Released fins for advanced integrated circuit structure fabrication are described. For example, an integrated circuit structure includes a sub-fin. A dielectric spacer material is on the sub-fin. A fin is on the dielectric spacer material. A void in the dielectric spacer material, the void vertically between the sub-fin and the fin.
1 . An integrated circuit structure, comprising:
a sub-fin adjacent to a trench isolation structure;
a dielectric spacer material on the sub-fin, the dielectric spacer material over and in contact with a top surface of the trench isolation structure, and the dielectric spacer material separate and distinct from the trench isolation structure;
a fin on the dielectric spacer material; and
a void in the dielectric spacer material, the void vertically between the sub-fin and the fin.
2 . The integrated circuit structure of claim 1 , further comprising a gate structure over the fin.
3 . The integrated circuit structure of claim 1 , wherein the dielectric spacer material comprises silicon nitride.
4 . The integrated circuit structure of claim 1 , wherein the fin comprises a plurality of horizontally stacked nanowires.
5 . The integrated circuit structure of claim 1 , wherein the fin is a unitary body.
6 . A method of fabricating an integrated circuit structure, the method comprising:
forming a fin along a first direction, the fin on a sacrificial layer on a sub-fin, the sub-fin adjacent to a trench isolation structure;
forming a plurality of gate structures over the fin, individual ones of the plurality of gate structures along a second direction orthogonal to the first direction;
subsequent to forming the plurality of gate structures, removing the sacrificial layer to release the fin; and
forming a dielectric spacer material between the released fin and the sub-fin, the dielectric spacer material over and in contact with a top surface of the trench isolation structure, and the dielectric spacer material separate and distinct from the trench isolation structure.
7 . The method of claim 6 , wherein forming the dielectric spacer material between the released fin and the sub-fin comprises forming a void in the dielectric spacer material, the void vertically between the sub-fin and the fin.
8 . The method of claim 6 , wherein the fin comprises a plurality of horizontally stacked nanowires.
9 . The method of claim 6 , wherein the fin is a unitary body.
10 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising:
a sub-fin adjacent to a trench isolation structure;
a dielectric spacer material on the sub-fin, the dielectric spacer material over and in contact with a top surface of the trench isolation structure, and the dielectric spacer material separate and distinct from the trench isolation structure;
a fin on the dielectric spacer material; and
a void in the dielectric spacer material, the void vertically between the sub-fin and the fin.
11 . The computing device of claim 10 , further comprising:
a memory coupled to the board.
12 . The computing device of claim 10 , further comprising:
a communication chip coupled to the board.
13 . The computing device of claim 10 , wherein the component is a packaged integrated circuit die.
14 . The computing device of claim 10 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
15 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure fabricated according to a method comprising:
forming a fin along a first direction, the fin on a sacrificial layer on a sub-fin, the sub-fin adjacent to a trench isolation structure;
forming a plurality of gate structures over the fin, individual ones of the plurality of gate structures along a second direction orthogonal to the first direction;
subsequent to forming the plurality of gate structures, removing the sacrificial layer to release the fin; and
forming a dielectric spacer material between the released fin and the sub-fin, the dielectric spacer material over and in contact with a top surface of the trench isolation structure, and the dielectric spacer material separate and distinct from the trench isolation structure.
16 . The computing device of claim 15 , further comprising:
a memory coupled to the board.
17 . The computing device of claim 15 , further comprising:
a communication chip coupled to the board.
18 . The computing device of claim 15 , wherein the component is a packaged integrated circuit die.
19 . The computing device of claim 15 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.