IP Library Granted Patent US 12,500,209
Granted Patent B2
US 12,500,209 · App. 17/362,712 · Granted Dec 16, 2025

Embedded organic interposer for high bandwidth

Inventors: Javier A. Delacruz (San Jose, CA); Belgacem Haba (Saratoga, CA)
Assignee: Adeia Semiconductor Technologies LLC
H01L25/0655H01L23/49894H01L23/5383H01L25/16H01L25/50H05K1/0243H05K3/4694H01L23/15H01L23/5384H01L25/18H05K1/185H05K2201/09227H05K2201/10015H05K2201/10159H05K2201/10522H05K2201/10674
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Quick Facts
Patent No.
US 12,500,209
App. No.
17/362,712
Granted
Dec 16, 2025
Kind
B2
Abstract

Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.

Claims (32)

1 . A microelectronic apparatus, comprising:

a substrate comprising at least one core layer, the at least one core layer comprising an inorganic material;

an interposer for electrically connecting microelectronic components, the interposer comprising:

a plurality of parallel organic dielectric layers; and

a plurality of routing layers, each of the routing layers disposed between adjacent ones of the organic dielectric layers, each of the routing layers comprising horizontal traces, wherein:

the interposer is embedded in the at least one core layer, the at least one core layer and the interposer defining a horizontal substrate surface that is parallel to the horizontal traces; and

each horizontal trace comprises a conductor having a cross-section for providing a data transfer rate of at least 1 gigabit per second between a first microelectronic component and a second microelectronic component; and

a build-up layer disposed vertically adjacent to the horizontal substrate surface, wherein the build-up layer comprises conductors for connecting the microelectronic components to the horizontal traces.

2 . The microelectronic apparatus of claim 1 , wherein the organic dielectric layers comprise an organic polymer.

3 . The microelectronic apparatus of claim 1 , wherein the organic dielectric layers comprise an epoxy or a glass-reinforced epoxy laminate.

4 . The microelectronic apparatus of claim 1 , wherein the organic dielectric layers comprise a bismaleimide-triazine resin.

5 . The microelectronic apparatus of claim 1 , wherein the organic dielectric layers are free from silicon.

6 . The microelectronic apparatus of claim 1 , wherein the horizontal traces and the conductors connect two or more microelectronic components disposed on the build-up layer.

7 . The microelectronic apparatus of claim 1 , wherein the core layer comprises ceramic.

8 . The microelectronic apparatus of claim 1 , wherein the horizontal traces have a cross-sectional width of 2-10 microns parallel to the horizontal substrate surface.

9 . The microelectronic apparatus of claim 1 , wherein the parallel organic dielectric layers have a thickness of 2-10 microns orthogonal to the horizontal substrate surface.

10 . The microelectronic apparatus of claim 1 , wherein the microelectronic components are memory stacks.

11 . The microelectronic apparatus of claim 1 , wherein the interposer comprises a laminate stack of parallel and interleaved organic dielectric layers and routing layers.

12 . The microelectronic apparatus of claim 1 , further comprising:

a capacitor embedded in the at least one core layer, the capacitor being horizontally adjacent to the interposer.

13 . The microelectronic apparatus of claim 1 , wherein a pitch between horizontal traces in the routing layer is 2-10 microns and portions of the organic dielectric layers are disposed between the horizontal traces.

14 . The microelectronic apparatus of claim 13 , wherein the horizontal traces have a cross-sectional thickness of 1-7 microns orthogonal to the horizontal substrate surface.

15 . A microelectronic apparatus comprising:

an interposer embedded in a core layer of the microelectronic apparatus, the interposer and the core layer defining a horizontal surface, the interposer comprising:

a plurality of parallel organic dielectric layers; and

a plurality of routing layers, each of the routing layers disposed between adjacent ones of the organic dielectric layers, and each of the routing layers comprising horizontal traces, wherein:

each horizontal trace comprises a conductor having a cross-section for providing a data transfer rate of at least 1 gigabit per second between a first microelectronic component and a second microelectronic component; and

the horizontal traces are parallel to the horizontal surface; and

a build-up layer disposed vertically adjacent to the horizontal surface, wherein the build-up layer comprises conductors for connecting the first and second microelectronic components to the horizontal traces.

16 . The interposer of claim 15 , wherein the organic dielectric layers comprise an organic polymer, an epoxy, a glass-reinforced epoxy laminate or a bismaleimide-triazine resin.

17 . The interposer of claim 15 , wherein the horizontal traces have a cross-sectional thickness of 1-7 microns orthogonal to a horizontal interposer surface.

18 . The interposer of claim 15 , wherein the horizontal traces have a cross-sectional width of 2-10 microns parallel to a horizontal interposer surface.

Assignments (4)
CHANGE OF NAME Recorded Mar 6, 2024
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 066743/0506 →
SECURITY INTEREST Recorded May 19, 2023
From: ADEIA GUIDES INC.; ADEIA MEDIA HOLDINGS LLC; ADEIA MEDIA SOLUTIONS INC.; ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR SOLUTIONS LLC; ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 063707/0884 →
CHANGE OF NAME Recorded Aug 3, 2022
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 061067/0634 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2021
From: DELACRUZ, JAVIER A.; HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 056710/0072 →
Continuity (3)
Continuation 16555127 · Aug 29, 2019
Continuation 15499557 · Apr 27, 2017
Related Publication 20210327851A1 · Oct 21, 2021
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