Semiconductor devices including a lower semiconductor package, an upper semiconductor package on the lower semiconductor package, and a connection pattern between the lower semiconductor package and the upper semiconductor package

1. A semiconductor device, comprising:

a lower semiconductor package, the lower semiconductor package including a lower base and a first lower chip on the lower base, the first lower chip including a chip pad, a pad structure, a heat sink structure and a redistribution line configured to electrically connect the chip pad and the pad structure to each other;

an upper semiconductor package including at least one chip and on the lower semiconductor package; and

a connection pattern between the lower semiconductor package and the upper semiconductor package, the connection pattern configured to electrically connect the lower semiconductor package and the upper semiconductor package to each other, the connection pattern connected to the upper semiconductor package, the connection pattern extending away from the upper semiconductor package to be connected to the pad structure,

wherein the chip pad does not overlap the pad structure and the connection pattern in a vertical direction perpendicular to an upper surface of the lower base.

2. The semiconductor device of claim 1 , wherein

the pad structure includes

a first pad, and

a second pad on the first pad,

a top surface of the second pad of the pad structure is at a higher level than a top surface of the chip pad,

the top surface of the chip pad is at a same height level as a top surface of the first pad, and

a bottom surface of the chip pad is at a same height level as a bottom surface of the first pad.

3. The semiconductor device of claim 2 , wherein

the heat sink structure includes a first heat sink pattern and a second heat sink pattern on the first heat sink pattern,

a lower surface of the first heat sink pattern is at a same height level as a lower surface of the first pad,

the first heat sink pattern includes a same material as the first pad,

a lower surface of the second heat sink pattern is at a same height level as a lower surface of the second pad, and

the second heat sink pattern includes a same material as the second pad.

4. The semiconductor device of claim 1 , wherein

the pad structure includes

a first pad, and

a second pad on the first pad, and

the chip pad, the redistribution line and the first pad are included in a single, continuous instance of material.

5. The semiconductor device of claim 1 , wherein

the first lower chip further includes

a silicon substrate,

a lower layer on the silicon substrate,

an upper layer on the lower layer, and

an intermediate layer between the lower layer and the upper layer,

the chip pad, the pad structure, and the heat sink structure are on the lower layer, and

the upper layer and the intermediate layer have

a first opening that extends through both the upper layer and the intermediate layer to expose at least a portion of the chip pad, and

a second opening that extends through both the upper layer and the intermediate layer to expose at least a portion of a top surface of the pad structure.

6. The semiconductor device of claim 1 , wherein

the lower base includes a first base pad,

the lower semiconductor package further includes a wire configured to electrically connect the chip pad and the first base pad to each other, and

the lower semiconductor package further includes a lower mold layer covering the first lower chip and the wire.

7. The semiconductor device of claim 6 , further comprising:

a second lower chip between the first lower chip and the lower base;

an adhesive layer between the first lower chip and the second lower chip; and

a conductive bump between the second lower chip and the lower base,

wherein the adhesive layer is in contact with a bottom surface of a silicon substrate of the first lower chip and a top surface of the second lower chip.

8. The semiconductor device of claim 6 , wherein

the lower mold layer has a first opening extending through at least a portion of the lower mold layer to expose at least a portion of a top surface of the pad structure, and

the connection pattern extends away from the upper semiconductor package to be connected to the portion of the pad structure that is exposed by the first opening of the lower mold layer.

9. A semiconductor device, comprising:

a lower semiconductor package;

an upper semiconductor package including at least one chip and on the lower semiconductor package; and

a connection pattern between the lower semiconductor package and the upper semiconductor package, and configured to electrically connect the lower semiconductor package and the upper semiconductor package to each other,

wherein the lower semiconductor package includes:

a lower base;

a first lower chip on the lower base; and

a mold layer on the lower base and contacting a side surface of the first lower chip,

wherein the first lower chip includes:

a substrate;

a first insulating layer on the substrate;

a chip pad on the first insulating layer;

a pad structure on the first insulating layer and including a first pad and a second pad on the first pad;

a redistribution line on the first insulating layer and configured to electrically connect the chip pad and the pad structure;

a heat sink structure on the first insulating layer; and

a second insulating layer on the first insulating layer, contacting a first portion of the chip pad, a portion of the pad structure and a portion of the redistribution line, and covering at least an upper surface of the redistribution line, and

wherein at least a portion of the heat sink structure is at a same height level as at least a second portion of the pad structure.

10. The semiconductor device of claim 9 , wherein

the lower semiconductor package further includes an upper insulating layer on the second insulating layer, and

wherein the second pad penetrates through the upper insulating layer and the second insulating layer and contacts the first pad.

11. The semiconductor device of claim 10 , wherein

the mold layer further includes a portion on an upper surface of the upper insulating layer, and

wherein the connection pattern penetrates through the portion of the mold layer and contacts the second pad.

12. The semiconductor device of claim 9 , wherein

the redistribution line extends from the first pad and the chip pad, and

the second insulating layer contacts a side surface and the upper surface of the redistribution line.

13. The semiconductor device of claim 9 , wherein a thickness of the second pad is greater than a thickness of the first pad.

14. The semiconductor device of claim 9 , wherein a top surface of the second pad is at a higher level than a top surface of the chip pad.

15. The semiconductor device of claim 9 , wherein the lower semiconductor package further includes a second lower chip between the first lower chip and the lower base.

16. A semiconductor device, comprising:

a lower semiconductor package;

an upper semiconductor package including at least one chip and on the lower semiconductor package; and

a connection pattern between the lower semiconductor package and the upper semiconductor package, and configured to electrically connect the lower semiconductor package and the upper semiconductor package to each other,

wherein the lower semiconductor package includes:

a lower base;

a first lower chip on the lower base; and

a mold layer on the lower base and contacting a side surface of the first lower chip,

wherein the first lower chip includes:

a chip pad;

a pad structure including a first pad and a second pad on the first pad; and

a redistribution line configured to electrically connect the chip pad and the first pad;

a heat sink structure,

wherein the chip pad and the first pad are each at a same height level as the redistribution line,

wherein at least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure,

wherein the mold layer includes a portion overlapping a top surface of the redistribution line, and

wherein the connection pattern contacts the second pad.

17. The semiconductor device of claim 16 , wherein

the first lower chip further includes a silicon substrate and an insulating layer on the silicon substrate,

the chip pad, the pad structure, the redistribution line and the heat sink structure are on the insulating layer, and

the mold layer contacts a side surface of the silicon substrate.

18. The semiconductor device of claim 16 , wherein the lower semiconductor package further includes a second lower chip between the first lower chip and the lower base.

19. The semiconductor device of claim 16 , wherein

a distance between the chip pad and a center of the first lower chip is greater than a distance between the pad structure and the center of the first lower chip, and

the distance between the pad structure and the center of the first lower chip is greater than a distance between the heat sink structure and the center of the first lower chip.