Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
1. An integrated circuit block comprising:
a first node;
a second node; and
a series arrangement of three or more field-effect transistors (FET);
wherein:
i) the three or more FETs are configured to:
a) be connected in series with a series arrangement of one or more capacitors to couple a combination of the one or more capacitors and the three or more FETs between the first node and the second node;
b) withstand a voltage greater than a voltage withstood by one FET of the three or more FETs; and
c) receive a control signal to enable or disable the FETs thereby adjusting the capacitance between the first node and the second node, and
ii) one or more compensation capacitors are coupled to a drain terminal of at least one of the three or more FETs.
2. The integrated circuit block of claim 1 , wherein the one or more compensation capacitors are coupled to a source terminal of the at least one of the three or more FETs.
3. The integrated circuit block of claim 1 , wherein the compensation capacitors comprise metal-based capacitors.
4. The integrated circuit block of claim 1 , wherein the one or more compensation capacitors comprise a first compensation capacitor coupled across drain and source terminals of a first FET of the three or more FETs and a second compensation capacitor coupled across drain and source terminals of a second FET of the three or more FETs.
5. The integrated circuit block of claim 4 , wherein the first FET is a top FET in the series arrangement and wherein the first compensation capacitor has a capacitance value higher than the second compensation capacitor.
6. The integrated circuit block of claim 4 , wherein the second FET is a bottom FET in the series arrangement and wherein the first compensation capacitor has a capacitance value lower than the second compensation capacitor.
7. A digitally tuned capacitor (DTC) comprising a plurality of the integrated circuit blocks of claim 1 , wherein the plurality of the integrated circuit blocks are configured in parallel.
8. An integrated circuit block comprising:
a first node;
a second node; and
a series arrangement of two or more field-effect transistors (FET), wherein:
i) the two or more FETs are configured to:
a) be connected in series with a series arrangement of one or more capacitors to couple a combination of the one or more capacitors and the two or more FETs between the first node and the second node; and
b) withstand a voltage greater than a voltage withstood by one FET of the two or more FETs;
ii) each of the two or more FETs has a control node configured to receive a control signal to enable or disable the two or more FETs, and thereby adjusting the capacitance between the first node and the second node; and
iii) compensation capacitors are coupled to a drain terminal of at least one of the two or more FETs.
9. The integrated circuit block of claim 8 , wherein the compensation capacitors are coupled to a source terminal of the at least one the two or more FETs.
10. The integrated circuit block of claim 8 , wherein the compensation capacitors comprise metal-based capacitors.
11. A digitally tuned capacitor (DTC) comprising a plurality of the integrated circuit blocks of claim 10 , wherein the plurality of the integrated circuit blocks are configured in parallel.
12. The integrated circuit block of claim 8 , wherein the one or more compensation capacitors comprise a first compensation capacitor coupled across drain and source terminals of a first FET of the two or more FETs and a second compensation capacitor coupled across drain and source terminals of a second FET of the two or more FETs.
13. The integrated circuit block of claim 12 , wherein the first FET is a top FET in the series arrangement and wherein the first compensation capacitor has a capacitance value higher than the second compensation capacitor.
14. The integrated circuit block of claim 12 , wherein the second FET is a bottom FET in the series arrangement and wherein the first compensation capacitor has a capacitance value lower than the second compensation capacitor.
15. An integrated circuit block comprising:
a first node;
a second node;
a series arrangement of one or more capacitors;
a series arrangement of a plurality of field-effect transistors (FET), and a first compensation capacitor; and wherein:
the one or more capacitors are in series with the plurality of FETs;
a combination of the one or more capacitors and the plurality of FETs is coupled between the first node and the second node;
the plurality of FETs are configured to withstand a voltage greater than a voltage withstood by one FET;
the plurality of FETs are configured to receive a control signal to enable or disable the FETs, thereby adjusting the capacitance between the two nodes, and
the first compensation capacitor is connected to a drain terminal of one or more FETs of the plurality of FETs.
16. The integrated circuit block of claim 15 , wherein the first compensation capacitor is connected to a source terminal of the one or more FETs of the plurality of FETs.
17. The integrated circuit block of claim 16 , wherein the first compensation capacitors comprises a metal-based capacitor.
18. The integrated circuit block of claim 16 , wherein the first compensation capacitor and the plurality of FETs are integrated on a same chip.
19. The integrated circuit block of claim 18 , wherein the first compensation capacitor is physically located on a side of or above the plurality of FETs on the chip.
20. The integrated circuit block of claim 16 , further comprising a second compensation capacitor, wherein the first compensation capacitor is coupled across drain and source terminals of a first FET of the plurality of FETs and the second compensation capcitor is coupled across drain and source terminals of a second FET of the plurality of FETs.
21. The integrated circuit block of claim 20 , wherein the first FET is a top FET in the series arrangement and wherein the first compensation capacitor has a capacitance value higher than the second compensation capacitor.
22. The integrated circuit block of claim 20 , wherein the second FET is a bottom FET in the series arrangement and wherein the first compensation capacitor has a capacitance value lower than the second compensation capacitor.