Power rail and signal line arrangement in integrated circuits having stacked transistors

1. An integrated circuit device comprising:

a first-type active-region semiconductor structure extending in a first direction;

a first gate-conductor, extending in a second direction perpendicular to the first direction, intersecting the first-type active-region semiconductor structure at a channel region of a first-type transistor;

a second-type active-region semiconductor structure, extending in the first direction, stacked with the first-type active-region semiconductor structure and shifted from the first-type active-region semiconductor structure along a third direction that is perpendicular to both the first direction and the second direction;

a second gate-conductor, extending in the second direction, intersecting the second-type active-region semiconductor structure at a channel region of a second-type transistor;

a front-side conductive layer, oriented toward the third direction, positioned above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure;

a back-side conductive layer, oriented toward the third direction, positioned below the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, wherein the back-side conductive layer is a single layer;

a front-side power rail extending in the first direction, in the front-side conductive layer, configured to maintain a first supply voltage;

a back-side power rail extending in the first direction, in the back-side conductive layer, configured to maintain a second supply voltage;

a front-side signal line extending in the first direction, in the front-side conductive layer;

a back-side signal line extending in the first direction, in the back-side conductive layer;

a first source conductive segment, extending in the second direction, intersecting the first-type active-region semiconductor structure at a source region of the first-type transistor, and conductively connected to the front-side power rail through a first via-connector;

a second source conductive segment, extending in the second direction, intersecting the second-type active-region semiconductor structure at a source region of the second-type transistor, and conductively connected to the back-side power rail through a second via-connector; and

a drain conductive segment, extending in the second direction, intersecting one or both of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, and conductively connected to the front-side signal line or the back-side signal line through a third via-connector.

2. The integrated circuit device of claim 1 , wherein the first gate-conductor is joined with the second gate-conductor and forms a third gate-conductor.

3. The integrated circuit device of claim 1 , wherein the first gate-conductor is separated from the second gate-conductor along the third direction by a gate-stack insulator.

4. The integrated circuit device of claim 1 , wherein the front-side power rail and the back-side power rail overlap each other when viewed along the third direction.

5. The integrated circuit device of claim 1 , wherein the front-side power rail and the back-side power rail are aligned with each other along boundaries when viewed along the third direction.

6. An integrated circuit device comprising:

a first-type active-region semiconductor structure extending in a first direction;

a second-type active-region semiconductor structure, extending in the first direction, stacked with the first-type active-region semiconductor structure;

a front-side conductive layer above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure;

a back-side conductive layer below the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, wherein the back-side conductive layer is a single layer;

a plurality of gate-conductors, extending in a second direction perpendicular to the first direction, each gate-conductor in the plurality of gate-conductors intersecting one or both of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure while forming a gate terminal of at least one transistor;

a plurality of conductive segments, extending in the second direction, each conductive segment in the plurality of conductive segments intersecting one or both of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure while forming a source terminal or a drain terminal of at least one transistor, and wherein the plurality of conductive segments includes a first conductive segment, a second conductive segment, a third conductive segment intersecting the first-type active-region semiconductor structure, and a fourth conductive segment intersecting the second-type active-region semiconductor structure;

a front-side signal line extending in the first direction, in the front-side conductive layer, and configured to transmit a first voltage change at the first conductive segment to one or more of the gate-conductors or to one or more of the conductive segments;

a back-side signal line extending in the first direction, in the back-side conductive layer, and configured to transmit a second voltage change at the second conductive segment to one or more of the gate-conductors or to one or more of the conductive segments;

a front-side power rail extending in the first direction, in the front-side conductive layer, configured to maintain a first supply voltage, and conductively connected to the third conductive segment through a first via-connector; and

a back-side power rail extending in the first direction, in the back-side conductive layer, configured to maintain a second supply voltage, and conductively connected to the fourth conductive segment through a second via-connector.

7. The integrated circuit device of claim 6 , wherein the front-side power rail and the back-side power rail overlaps with each other when viewed in a direction that is normal to the front-side conductive layer and the back-side conductive layer.

8. The integrated circuit device of claim 6 , wherein the front-side power rail and the back-side power rail are aligned with each other along boundaries when viewed in a direction that is normal to the front-side conductive layer and the back-side conductive layer.

9. The integrated circuit device of claim 6 , wherein the first-type active-region semiconductor structure is underneath the second-type active-region semiconductor structure.

10. The integrated circuit device of claim 6 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-sheet.

11. The integrated circuit device of claim 6 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-wire.

12. The integrated circuit device of claim 1 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-sheet.

13. The integrated circuit device of claim 1 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-wire.

14. An integrated circuit device comprising:

a first-type active-region semiconductor structure extending in a first direction;

a first gate-conductor, extending in a second direction perpendicular to the first direction, intersecting the first-type active-region semiconductor structure at a channel region of a first-type transistor;

a second-type active-region semiconductor structure, extending in the first direction, stacked with the first-type active-region semiconductor structure and shifted from the first-type active-region semiconductor structure along a third direction that is perpendicular to both the first direction and the second direction;

a second gate-conductor, extending in the second direction, intersecting the second-type active-region semiconductor structure at a channel region of a second-type transistor;

a front-side conductive layer, oriented toward the third direction, positioned above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure;

a back-side conductive layer, oriented toward the third direction, positioned below the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, wherein the back-side conductive layer is a single layer;

a front-side power rail extending in the first direction, in the front-side conductive layer, configured to maintain a first supply voltage;

a back-side power rail extending in the first direction, in the back-side conductive layer, configured to maintain a second supply voltage;

a front-side signal line extending in the first direction, in the front-side conductive layer;

a back-side signal line extending in the first direction, in the back-side conductive layer;

a first source conductive segment, extending in the second direction, intersecting the first-type active-region semiconductor structure at a source region of the first-type transistor, and conductively connected to the front-side power rail through a first via-connector; and

a second source conductive segment, extending in the second direction, intersecting the second-type active-region semiconductor structure at a source region of the second-type transistor, and conductively connected to the back-side power rail through a second via-connector.

15. The integrated circuit device of claim 14 , wherein the first gate-conductor is joined with the second gate-conductor and forms a third gate-conductor.

16. The integrated circuit device of claim 14 , wherein the first gate-conductor is separated from the second gate-conductor along the third direction by a gate-stack insulator.

17. The integrated circuit device of claim 14 , wherein the front-side power rail and the back-side power rail overlap each other when viewed along the third direction.

18. The integrated circuit device of claim 14 , wherein the front-side power rail and the back-side power rail are aligned with each other along boundaries when viewed along the third direction.

19. The integrated circuit device of claim 14 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-sheet.

20. The integrated circuit device of claim 14 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-wire.