Power rail and signal line arrangement in integrated circuits having stacked transistors
An integrated circuit device includes a first-type transistor having a channel region in a first-type active-region semiconductor structure and a second-type transistor having a channel region in a second-type active-region semiconductor structure which is stacked with the first-type active-region semiconductor structure. In the integrated circuit, a front-side power rail and a front-side signal line in a front-side conductive layer extend in the first direction is, and a back-side power rail and a back-side signal line in a back-side conductive layer also extend in the first direction. The front-side conductive layer is above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, while the back-side conductive layer is below the first-type active-region semiconductor structure and the second-type active-region semiconductor structure.
1 . An integrated circuit device comprising:
a substrate;
a first-type active-region semiconductor structure extending in a first direction at a front side of the substrate;
a first-type transistor having a channel region in the first-type active-region semiconductor structure;
a second-type active-region semiconductor structure extending in the first direction at the front side of the substrate and stacked with the first-type active-region semiconductor structure;
a second-type transistor having a channel region in the second-type active-region semiconductor structure, wherein the first-type transistor and the second-type transistor are stacked over one another and form one complementary pair of transistors;
a front-side power rail and a front-side signal line each extending in the first direction in a front-side conductive layer which is above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, wherein the front-side power rail is connected to a source terminal of the first-type transistor in the one complementary pair of transistors and is configured to maintain a first supply voltage; and
a back-side power rail and a back-side signal line each extending in the first direction in a back-side conductive layer at a back side of the substrate, wherein the front-side power rail and the back-side power rail overlap each other when viewed in a direction that is normal to the front-side conductive layer and the back-side conductive layer, wherein the back-side power rail is connected to a source terminal of the second-type transistor in the one complementary pair of transistors and is configured to maintain a second supply voltage, and wherein the back-side conductive layer is a single layer, wherein the back-side signal line is either configured to receive a voltage change at a drain terminal of the second-type transistor or configured to apply a voltage change to a gate terminal of the second-type transistor, and wherein the back-side signal line and the back-side power rail are in a same conductive layer.
2 . The integrated circuit device of claim 1 , further comprising:
a first gate-conductor, extending in a second direction perpendicular to the first direction, intersecting the first-type active-region semiconductor structure at the channel region of the first-type transistor.
3 . The integrated circuit device of claim 2 , further comprising:
a first source conductive segment, extending in the second direction, intersecting the first-type active-region semiconductor structure at a source region of the first-type transistor, and conductively connected to the front-side power rail through a first via-connector.
4 . The integrated circuit device of claim 1 , wherein the front-side power rail and the back-side power rail are aligned with each other along boundaries when viewed in a direction that is normal to the front-side conductive layer and the back-side conductive layer.
5 . The integrated circuit device of claim 1 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-sheet.
6 . The integrated circuit device of claim 1 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-wire.
7 . An integrated circuit device comprising:
a substrate;
a first-type active-region semiconductor structure extending in a first direction at a front side of the substrate;
first-type transistors each having a channel region in the first-type active-region semiconductor structure;
a second-type active-region semiconductor structure, extending in the first direction at the front side of the substrate, stacked with the first-type active-region semiconductor structure;
second-type transistors each having a channel region in the second-type active-region semiconductor structure, wherein a first-type transistor and a second-type transistor are stacked over one another and form one complementary pair of transistors;
a front-side power rail extending in the first direction in a front-side conductive layer above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, wherein the front-side power rail is connected to a source terminal of the first-type transistor in the one complementary pair of transistors;
a front-side signal line extending in the first direction in the front-side conductive layer, wherein the front-side signal line is configured to receive a first voltage change at a drain terminal of one of the first-type transistors;
a back-side power rail extending in the first direction in a back-side conductive layer at a back side of the substrate, wherein the front-side power rail and the back-side power rail overlaps with each other when viewed in a direction that is normal to the front-side conductive layer and the back-side conductive layer, and wherein the back-side power rail is connected to a source terminal of the second-type transistor in the one complementary pair of transistors; and
a back-side signal line extending in the first direction in the back-side conductive layer, wherein the back-side signal line is configured to receive a second voltage change at a drain terminal of one of the second-type transistors, and wherein the back-side signal line and the back-side power rail are in a same conductive layer.
8 . The integrated circuit device of claim 7 , wherein the front-side power rail and the back-side power rail are aligned with each other along boundaries when viewed in a direction that is normal to the front-side conductive layer and the back-side conductive layer.
9 . The integrated circuit device of claim 7 , wherein the first-type active-region semiconductor structure is underneath the second-type active-region semiconductor structure.
10 . The integrated circuit device of claim 7 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-sheet.
11 . The integrated circuit device of claim 7 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-wire.
12 . An integrated circuit device comprising:
a substrate;
a first-type active-region semiconductor structure extending in a first direction at a front side of the substrate;
a second-type active-region semiconductor structure extending in the first direction at the front side of the substrate and stacked with the first-type active-region semiconductor structure;
a first source conductive segment, extending in a second direction, intersecting the first- type active-region semiconductor structure at a source region of a first-type transistor, wherein the second direction is perpendicular to the first direction;
a second source conductive segment, extending in the second direction, intersecting the second-type active-region semiconductor structure at a source region of a second-type transistor, wherein the first-type transistor and the second-type transistor are stacked over one another and form one complementary pair of transistors;
a front-side power rail and a front-side signal line each extending in the first direction in a front-side conductive layer which is above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure; and
a back-side power rail and a back-side signal line each extending in the first direction in a back-side conductive layer at a back side of the substrate, wherein the front-side power rail and the back-side power rail overlap each other when viewed in a direction that is normal to the front-side conductive layer and the back-side conductive layer, wherein the back-side conductive layer is a single layer, wherein the back-side signal line is either configured to receive a voltage change at a drain terminal of the second-type transistor or configured to apply a voltage change to a gate terminal of the second-type transistor, and wherein the back-side signal line and the back-side power rail are in a same conductive layer;
a first via-connector connected between the front-side power rail and the first source conductive segment which is connected to the source region of the first-type transistor in the one complementary pair of transistors; and
a second via-connector connected between the back-side power rail and the second source conductive segment which is connected to the source region of the second-type transistor in the one complementary pair of transistors.
13 . The integrated circuit device of claim 12 , further comprising:
a first gate-conductor, extending in the second direction perpendicular to the first direction, intersecting the first-type active-region semiconductor structure at a channel region of the first-type transistor.
14 . The integrated circuit device of claim 13 , further comprising:
a drain conductive segment, extending in the second direction, intersecting ene or both of the first-type active-region semiconductor structure.
15 . The integrated circuit device of claim 12 , wherein the front-side power rail and the back-side power rail are aligned with each other along boundaries when viewed in a direction that is normal to the front-side conductive layer and the back-side conductive layer.
16 . The integrated circuit device of claim 12 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-sheet.
17 . The integrated circuit device of claim 12 , wherein each of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure includes at least one nano-wire.
18 . The integrated circuit device of claim 2 , further comprising:
a second gate-conductor, extending in the second direction, intersecting the second-type active-region semiconductor structure at the channel region of the second-type transistor.
19 . The integrated circuit device of claim 18 , further comprising:
a second source conductive segment, extending in the second direction, intersecting the second-type active-region semiconductor structure at a source region of the second-type transistor, and conductively connected to the back-side power rail through a second via-connector.
20 . The integrated circuit device of claim 13 , further comprising:
a second gate-conductor, extending in the second direction, intersecting the second-type active-region semiconductor structure at a channel region of the second-type transistor; and
a drain conductive segment, extending in the second direction, intersecting one or both of the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, and conductively connected to the front-side signal line or the back-side signal line through a third via-connector.