Power rail and signal line arrangement in integrated circuits having stacked transistors
A method includes fabricating a first-type active-region semiconductor, depositing a layer of dielectric material covering the first-type active-region semiconductor structure, and fabricating a second-type active-region semiconductor structure atop the layer of dielectric material. The method includes forming a front-side power rail and a front-side signal line extending in the first direction in a front-side metal layer overlying a first insulating material that covers the first-type active-region semiconductor. The front-side power rail is conductively connected to a second source conductive segment intersecting the second-type active-region semiconductor structure. The method includes forming a back-side metal layer on a backside of the substrate, and forming a back-side power rail and a back-side signal line extending in the first direction in the back-side metal layer. The back-side power rail is conductively connected to a first source conductive segment intersecting the first-type active-region semiconductor structure.
1 . A method comprising:
fabricating a first-type active-region semiconductor structure extending in a first direction on a substrate;
fabricating a first gate-conductor intersecting the first-type active-region semiconductor structure at a channel region of a first first-type transistor;
fabricating a first source conductive segment intersecting the first-type active-region semiconductor structure at a first source region;
fabricating a first drain conductive segment intersecting the first-type active-region semiconductor structure at a first drain region;
depositing a layer of dielectric material covering at least the first-type active-region semiconductor structure;
fabricating a second-type active-region semiconductor structure extending in the first direction atop the layer of dielectric material, wherein the second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure;
fabricating a second gate-conductor intersecting the second-type active-region semiconductor structure at a channel region of a first second-type transistor;
fabricating a second source conductive segment intersecting the second-type active-region semiconductor structure at a second source region;
depositing a first insulating material covering the second gate-conductor and the second source conductive segment;
depositing a front-side metal layer over the first insulating material and patterning the front-side metal layer to form a front-side power rail extending in the first direction and a front-side signal line extending in the first direction, wherein the front-side power rail is conductively connected to the second source conductive segment through a first via-connector, and wherein the front-side signal line is conductively connected to the second gate-conductor through a front-side gate via-connector;
flipping the substrate having the first-type active-region semiconductor structure and the second-type active-region semiconductor structure thereon; and
forming a back-side metal layer on a backside of the substrate after flipping the substrate and patterning the back-side metal layer to form a back-side power rail extending in the first direction and a back-side signal line extending in the first direction, wherein the back-side power rail is conductively connected to the first source conductive segment through a second via-connector, and wherein the back-side signal line is conductively connected to the first drain conductive segment through a third via-connector.
2 . The method of claim 1 , where patterning the front-side metal layer comprises patterning the front-side metal layer to form a second front-side signal line extending in the first direction that is conductively connected to the second gate-conductor through a front-side gate via-connector.
3 . The method of claim 1 , where patterning the back-side metal layer comprises patterning the back-side metal layer to form a second back-side signal line extending in the first direction that is conductively connected to the first gate-conductor through a back-side gate via-connector.
4 . The method of claim 1 , further comprising:
fabricating a gate inter-connector passing through the layer of dielectric material to directly connect the second gate-conductor with the first gate-conductor.
5 . The method of claim 1 , further comprising:
fabricating a second drain conductive segment intersecting the second-type active-region semiconductor structure at a second drain region.
6 . The method of claim 5 , further comprising:
fabricating a conductive-segment inter-connector passing through the layer of dielectric material to directly connect the first drain conductive segment with the second drain conductive segment.
7 . The method of claim 5 , wherein fabricating the first drain conductive segment comprises fabricating the first drain conductive segment intersecting the first-type active-region semiconductor structure at the first drain region of the first first-type transistor.
8 . The method of claim 5 , wherein fabricating the first drain conductive segment comprises fabricating the first drain conductive segment intersecting the first-type active-region semiconductor structure at the first drain region of a second first-type transistor.
9 . The method of claim 1 , wherein fabricating the first source conductive segment comprises:
fabricating the first source conductive segment intersecting the first-type active-region semiconductor structure at the first source region of a second first-type transistor.
10 . A method comprising:
fabricating a first-type active-region semiconductor structure extending in a first direction on a substrate;
fabricating a first source conductive segment intersecting the first-type active-region semiconductor structure at a first source region;
fabricating a first drain conductive segment intersecting the first-type active-region semiconductor structure at a first drain region;
depositing a layer of dielectric material covering at least the first-type active-region semiconductor structure;
fabricating a second-type active-region semiconductor structure extending in the first direction atop the layer of dielectric material, wherein the second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure;
fabricating a second source conductive segment intersecting the second-type active-region semiconductor structure at a second source region;
depositing a first insulating material covering the second source conductive segment;
forming a first via-connector connecting to the second source conductive segment and passing through the first insulating material;
depositing a front-side metal layer over the first insulating material and patterning the front-side metal layer to form a front-side power rail extending in the first direction and a front-side signal line extending in the first direction, wherein the front-side power rail is conductively connected to the first via-connector;
forming a second via-connector connecting to the first source conductive segment and passing through the substrate;
forming a third via-connector connecting to the first drain conductive segment and passing through the substrate;
flipping the substrate having the first-type active-region semiconductor structure and the second-type active-region semiconductor structure thereon; and
forming a back-side metal layer on a backside of the substrate after flipping the substrate and patterning the back-side metal layer to form a back-side power rail extending in the first direction and a back-side signal line extending in the first direction, wherein the back-side power rail is conductively connected to the second via-connector, and wherein the back-side signal line is conductively connected to the third via-connector.
11 . The method of claim 10 , further comprising:
fabricating a first gate-conductor intersecting the first-type active-region semiconductor structure at a channel region of a first first-type transistor, before depositing the layer of dielectric material covering the first-type active-region semiconductor structure and also the first gate-conductor; and
where patterning the back-side metal layer comprises patterning the back-side metal layer to form a second back-side signal line extending in the first direction that is conductively connected to the first gate-conductor through a back-side gate via-connector.
12 . The method of claim 10 , further comprising:
fabricating a second gate-conductor intersecting the second-type active-region semiconductor structure at a channel region of a first second-type transistor, and depositing the first insulating material covering the second source conductive segment and also the second gate-conductor; and
where patterning the front-side metal layer comprises patterning the front-side metal layer to form a second front-side signal line extending in the first direction that is conductively connected to the second gate-conductor through a front-side gate via-connector.
13 . The method of claim 10 , further comprising:
fabricating a second drain conductive segment intersecting the second-type active-region semiconductor structure at a second drain region.
14 . The method of claim 13 , further comprising:
fabricating a conductive-segment inter-connector passing through the layer of dielectric material to directly connect the first drain conductive segment with the second drain conductive segment.
15 . The method of claim 13 , wherein fabricating the first drain conductive segment comprises fabricating the first drain conductive segment intersecting the first-type active-region semiconductor structure at the first drain region of a first first-type transistor.
16 . The method of claim 13 , wherein fabricating the first drain conductive segment comprises fabricating the first drain conductive segment intersecting the first-type active-region semiconductor structure at the first drain region of a second first-type transistor.
17 . The method of claim 10 , wherein fabricating the first source conductive segment comprises:
fabricating the first source conductive segment intersecting the first-type active-region semiconductor structure at the first source region of a second first-type transistor.
18 . A method comprising:
fabricating a first-type active-region semiconductor structure extending in a first direction on a substrate;
depositing a layer of dielectric material covering at least the first-type active-region semiconductor structure;
fabricating a second-type active-region semiconductor structure extending in the first direction atop the layer of dielectric material, wherein the second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure;
depositing a first insulating material covering at least the second-type active-region semiconductor structure;
forming a first via-connector passing through the first insulating material and connecting to a source terminal of a first second-type transistor in the second-type active-region semiconductor structure;
depositing a front-side metal layer over the first insulating material and patterning the front-side metal layer to form a front-side power rail extending in the first direction and a front-side signal line extending in the first direction, wherein the front-side power rail is conductively connected to the first via-connector;
forming a second via-connector passing through the substrate and connecting to a source terminal of a first first-type transistor in the first-type active-region semiconductor structure;
forming a third via-connector passing through the substrate and connecting to a drain terminal of the first first-type transistor in the first-type active-region semiconductor structure;
flipping the substrate having the first-type active-region semiconductor structure and the second-type active-region semiconductor structure thereon; and
forming a back-side metal layer on a backside of the substrate after flipping the substrate and patterning the back-side metal layer to form a back-side power rail extending in the first direction and a back-side signal line extending in the first direction, wherein the back-side power rail is conductively connected to the second via-connector, and wherein the back-side signal line is conductively connected to the third via-connector.
19 . The method of claim 18 , further comprising:
fabricating a second gate-conductor intersecting the second-type active-region semiconductor structure at a channel region of the first second-type transistor, and depositing the first insulating material covering the second-type active-region semiconductor structure and also the second gate-conductor; and
where patterning the front-side metal layer comprises patterning the front-side metal layer to form a second front-side signal line extending in the first direction that is conductively connected to the second gate-conductor through a front-side gate via-connector.
20 . The method of claim 18 , further comprising:
fabricating a first gate-conductor intersecting the first-type active-region semiconductor structure at a channel region of the first first-type transistor, before depositing the layer of dielectric material covering the first-type active-region semiconductor structure and also the first gate-conductor; and
where patterning the back-side metal layer comprises patterning the back-side metal layer to form a second back-side signal line extending in the first direction that is conductively connected to the first gate-conductor through a back-side gate via-connector.