Granted Patent B2

US 12,333,339 · App. 17/399,784 · Granted Jun 17, 2025

Inventors: Andrew M. Havlir (Orlando, FL); Ajay Simha Modugala (Orlando, FL); Benjamin Bowman (London, GB); Yunjun Zhang (Orlando, FL)

Assignee: Apple Inc.

G06F9/5027G06F9/4881

Abstract

Claims (68)

1. An apparatus, comprising:

first and second groups of graphics processor sub-units, wherein the first group of sub-units shares a first cache and the second group of sub-units shares a second cache;

distribution circuitry configured to:

receive a software-specified set of graphics work and a software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units; and

assign, based on the mapping, a first subset of the set of graphics work to the first group of graphics sub-units and a second subset of the set of graphics work to the second group of graphics sub-units; and

work sharing control circuitry configured to:

determine that another group of sub-units that share a cache have dispatched all of their assigned portion for the set of graphics work;

update a hardware-implemented finite state machine based on the determination, wherein the hardware finite state machine is implemented using sequential circuitry and combinational circuitry; and

override, based on the update to the hardware-implemented finite state machine, the software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units, wherein the override re-assigns part of the first subset of the set of graphics work from the first group of graphics units to the other group of sub-units and the part of the first subset would not have been assigned to the other group of sub-units under the software-indicated mapping.

2. The apparatus of claim 1 , wherein the apparatus includes control circuitry configured to store, in configuration registers, multiple mappings of portions of sets of graphics work to groups of graphics processor sub-units.

3. The apparatus of claim 1 , wherein the set of graphics work is a compute kernel.

4. The apparatus of claim 3 , wherein the distribution circuitry includes:

primary kernel walker circuitry configured to determine the portions of the compute kernel;

first group walker circuitry configured to iterate portions of the compute kernel assigned to the first group of graphics sub-units to determine batches of workgroups; and

second group walker circuitry configured to iterate portions of the compute kernel assigned to the second group of graphics sub-units to determine batches of workgroups.

5. The apparatus of claim 4 , wherein the distribution circuitry further includes:

group walker arbitration circuitry configured to select from among batches of workgroups determined by the first and second group walker circuitry; and

sub-unit assign circuitry configured to assign batches selected by the group walker arbitration circuitry to one or more graphics sub-units in the group of sub-units corresponding to the selected group walker circuitry.

6. The apparatus of claim 1 , wherein the apparatus supports mappings of portions of sets of graphics work to groups of graphics processor sub-units for multiple dimensionalities including single-dimension, two-dimensional, and three-dimensional.

7. The apparatus of claim 1 , further comprising:

circuitry that implements a plurality of logical slots, wherein a set of sub-units in the first and second groups each implement multiple distributed hardware slots; and

control circuitry configured to:

assign the set of graphics work to a first logical slot;

determine a distribution rule for the set of graphics work that indicates to whether distribute to all of the graphics processor sub-units in the set or to distribute to only a portion of the graphics processor sub-units; and

determine mappings between the first logical slot and respective sets of one or more distributed hardware slots based on the distribution rule and based on the mappings of portions of the set of graphics work to groups of graphics processor sub-units.

8. A non-transitory computer-readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:

first and second groups of graphics processor sub-units, wherein the first group of sub-units shares a first cache and the second group of sub-units shares a second cache;

distribution circuitry configured to:

receive a software-specified set of graphics work and a software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units; and

assign, based on the mapping, a first subset of the set of graphics work to the first group of graphics sub-units and a second subset of the set of graphics work to the second group of graphics sub-units; and

work sharing control circuitry configured to:

determine that another group of sub-units that share a cache have dispatched all of their assigned portion for the set of graphics work;

update a hardware-implemented finite state machine based on the determination wherein the hardware finite state machine is implemented using sequential circuitry and combinational circuitry; and

override, based on the update to the hardware-implemented finite state machine, the software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units, wherein the override re-assigns part of the first subset of the set of graphics work from the first group of graphics units to the other group of sub-units and the part of the first subset would not have been assigned to the other group of sub-units under the software-indicated mapping.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the circuit includes control circuitry configured to store, in configuration registers, multiple mappings of portions of sets of graphics work to groups of graphics processor sub-units.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the distribution circuitry includes:

primary walker circuitry configured to determine the portions of the set of graphics work;

first group walker circuitry configured to iterate portions of the set of graphics work assigned to the first group of graphics sub-units to determine subsets of the set of graphics work; and

second group walker circuitry configured to iterate portions of the set of graphics work assigned to the second group of graphics sub-units to determine subsets of the set of graphics work.

11. The non-transitory computer-readable storage medium of claim 10 , wherein the distribution circuitry further includes:

group walker arbitration circuitry configured to select from among subsets determined by the first and second group walker circuitry; and

sub-unit assign circuitry configured to assign batches selected by the group walker arbitration circuitry to one or more graphics sub-units in the group of sub-units corresponding to the selected group walker circuitry.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the circuit supports mappings of portions of sets of graphics work to groups of graphics processor sub-units for multiple dimensionalities of sets of graphics work including single-dimension, two-dimensional, and three-dimensional.

13. The non-transitory computer-readable storage medium of claim 8 , wherein the circuit further comprises:

circuitry that implements a plurality of logical slots, wherein a set of sub-units in the first and second groups each implement multiple distributed hardware slots; and

control circuitry configured to:

assign the set of graphics work to a first logical slot;

determine a distribution rule for the set of graphics work that indicates to whether distribute to all of the graphics processor sub-units in the set or to distribute to only a portion of the graphics processor sub-units; and

determine mappings between the first logical slot and respective sets of one or more distributed hardware slots based on the distribution rule and based on the mappings of portions of the set of graphics work to groups of graphics processor sub-units.

14. A method, comprising:

receiving, by distribution circuitry of a graphics processor that includes first and second groups of graphics processor sub-units, a software-specified set of graphics work and a software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units, wherein the first group of sub-units shares a first cache and the second group of sub-units shares a second cache;

assigning, by the distribution circuitry based on the mapping, a first subset of the set of graphics work to the first group of graphics sub-units and a second subset of the set of graphics work to the second group of graphics sub-units;

determining, by work sharing control circuitry of the graphics processor, that another group of sub-units that share a cache have dispatched all of their assigned portion for the set of graphics work;

updating, by the work sharing control circuitry, a hardware-implemented finite state machine based on the determination, wherein the hardware finite state machine is implemented using sequential circuitry and combinational circuitry; and

overriding, by the work sharing control circuitry based on the update to the hardware-implemented finite state machine, the software-indicated mapping of portions of the set of graphics work to groups of graphics processor sub-units, wherein the override re-assigns part of the first subset of the set of graphics work from the first group of graphics units to the other group of sub-units and the part of the first subset would not have been assigned to the other group of sub-units under the software-indicated mapping.

15. The method of claim 14 , further comprising:

disabling affinity-based work distribution in one or more modes of operation.

16. The method of claim 14 , further comprising:

assigning subsets of sets of graphics work to groups of graphics sub-units, based on multiple different mappings, wherein the multiple different mappings include mappings for at least two dimensionalities of sets of graphics work.

17. The method of claim 14 , wherein:

the graphics processor implements a plurality of logical slots;

the sub-units in the first and second groups each implement multiple distributed hardware slots; and

the method further includes specifying one or more software overrides to at least partially control a mapping between logical slots and respective sets of one or more distributed hardware slots for the set of graphics work.

18. The method of claim 17 , wherein the one or more software overrides include at least one of the following overrides:

mask information that indicates which sub-units are available to the set of graphics work;

a specified distribution rule that indicates distribution breadth;

group information that indicates a group of sub-units on which the set of graphics work should be deployed; and

policy information that indicates a scheduling policy.

Assignments (1)

Continuity (1)

References Cited (88)