Molded direct bonded and interconnected stack
Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.
1. A microelectronic assembly, comprising:
a first substrate having a first microelectronic circuit element in the first substrate;
a second substrate having a first bonding surface and a first microelectronic circuit element in the second substrate, the first bonding surface of the second substrate hybrid bonded to a bonding layer on the first substrate, coupling the first substrate to the second substrate and forming a stack;
a first encapsulant covering side edges of at least the second substrate of the stack, forming an encapsulated stack, the first encapsulant comprising multiple layers of encapsulating material;
a host substrate, the encapsulated stack directly bonded to the host substrate; and
a second encapsulant covering the encapsulated stack and covering at least side edges of the host substrate.
2. The microelectronic assembly of claim 1 , the host substrate further comprising at least one wirebond contact pad.
3. The microelectronic assembly of claim 1 , wherein the second encapsulant has a different composition than the first encapsulant.
4. The microelectronic assembly of claim 1 , wherein side edges of the first substrate are misaligned relative to the side edges of the second substrate.
5. The microelectronic assembly of claim 1 , further comprising a first conductive via electrically coupled to the first microelectronic circuit element of the first substrate and extending at least partially through the first substrate.
6. The microelectronic assembly of claim 5 , wherein the first substrate includes a second surface opposite the bonding layer, and wherein the first conductive via provides electrical connectivity to the second surface of the first substrate from the bonding layer on the first substrate.
7. The microelectronic assembly of claim 6 , further comprising a terminal connection coupled to the second surface of the first substrate and electrically coupled to the first conductive via.
8. The microelectronic assembly of claim 5 , wherein the second substrate includes a second bonding surface opposite the first bonding surface and a second microelectronic circuit element in the second substrate.
9. The microelectronic assembly of claim 8 , further comprising a second conductive via electrically coupled to the first and second microelectronic circuit elements of the second substrate and extending at least partially through the second substrate, the second conductive via provides electrical connectivity to the second bonding surface of the second substrate from the first bonding surface of the second substrate.
10. The microelectronic assembly of claim 9 , wherein the second conductive via provides electrical connectivity to the second bonding surface of the second substrate from a second surface of the first substrate opposite the bonding layer on the first substrate.
11. The microelectronic assembly of claim 8 , further comprising a third substrate having a first bonding surface and a first microelectronic circuit element in the third substrate, the first bonding surface of the third substrate bonded to the second bonding surface of the second substrate so that the first microelectronic circuit element of the third substrate is electrically coupled to the second microelectronic circuit element of the second substrate.
12. The microelectronic assembly of claim 11 , wherein the first encapsulant covers the side edges of the second and third substrates, but not the first substrate.
13. A microelectronic assembly comprising a plurality of the microelectronic assemblies of claim 11 .
14. The microelectronic assembly of claim 1 , wherein the multiple layers of encapsulating material comprises multiple different encapsulating materials.
15. The microelectronic assembly of claim 1 , wherein the first encapsulant comprises silica.
16. The microelectronic assembly of claim 1 , wherein the first encapsulant comprises a silicon compound.
17. The microelectronic assembly of claim 1 , wherein the first encapsulant comprises a molding compound.
18. The microelectronic assembly of claim 1 , wherein the first encapsulant covers side edges of the first substrate.
19. A microelectronic assembly, comprising:
a plurality of adjacent stacks of multiple microelectronic elements, each stack comprising:
a first substrate having a first microelectronic circuit element in the first substrate;
a second substrate having a first bonding surface and a first microelectronic circuit element in the second substrate, the first bonding surface of the second substrate hybrid bonded to a bonding layer on the first substrate, electrically coupling the first substrate to the second substrate without adhesive and forming a stack; and
a first encapsulant covering side edges of at least the second substrate of each stack, including the side edges facing side edges of an adjacent stack, the first encapsulant comprising multiple layers of encapsulating material.
20. The microelectronic assembly of claim 19 , further comprising a base substrate, the stack directly bonded to the base substrate.
21. The microelectronic assembly of claim 20 , further comprising a second encapsulant covering at least side edges of the first encapsulant and covering at least side edges of the base substrate.
22. The microelectronic assembly of claim 21 , wherein the second encapsulant has a different composition than the first encapsulant.
23. The microelectronic assembly of claim 21 , wherein the first encapsulant has a first particle content per volume, and the second encapsulant has a particle content per volume greater than the first particle content per volume.
24. The microelectronic assembly of claim 20 , further comprising at least one wirebond pad on a surface of the base substrate.
25. The microelectronic assembly of claim 24 , further comprising a non-molded die hybrid bonded without adhesive to the base substrate.
26. The microelectronic assembly of claim 19 , each stack further comprising:
a third substrate having a first bonding surface and a first microelectronic circuit element in the third substrate, the first bonding surface of the third substrate hybrid bonded to a second bonding surface of the second substrate opposite the first bonding surface, electrically coupling the third substrate to the second substrate without adhesive.
27. The microelectronic assembly of claim 26 , at least one stack further comprising:
a first conductive via electrically coupled to the first microelectronic circuit element of the first substrate and extending at least partially through the first substrate, a second conductive via electrically coupled to the first microelectronic circuit element of the second substrate and extending at least partially through the second substrate, and a third conductive via electrically coupled to the first microelectronic circuit element of the third substrate and extending at least partially through the third substrate, such that there is electrical connectivity from the first substrate to the third substrate.
28. The microelectronic assembly of claim 26 , wherein the first encapsulant covers the side edges of the second and third substrates of the at least one stack, but not the first substrate of the at least one stack.
29. The microelectronic assembly of claim 19 , wherein at least one of the first bonding surface and a second bonding surface opposite the first bonding surface of the second substrate of at least one stack includes an etched portion at a perimeter of the at least one of the first bonding surface and the second bonding surface forming an intentional recess at a perimeter edge of the second substrate.
30. The microelectronic assembly of claim 19 , wherein at least the second substrate comprises a solid-state memory device.