Top via containing random-access memory cross-bar array
Disclosed is a memory device. The memory device comprises a cross-bar array of memory cells. The cross-bar array of memory cells comprises a plurality of bottom level lines arranged in a first direction. The cross-bar array of memory cells further comprises a plurality of vias arranged on top of each of the plurality of bottom level lines. The cross-bar array of memory cells further comprises a plurality of memory cells. Each memory cell is arranged on top of one of the plurality of vias. The cross-bar array of memory cells further comprises a plurality of top level lines arranged in a second direction that is substantially perpendicular to the first direction. Each top level line is arranged on top of and electrically connected to two or more memory cells.
1. A memory cell comprising:
a bottom electrode that comprises a via arranged on top of a bottom line;
a memory stack arranged at least upon the via, wherein the memory stack comprises:
one or more memory layers that are configured to store data, the one or more memory layers in direct contact with a top surface and in direct contact with a lateral side(s) of the via; and
an isolation layer in contact with the one or more memory layers;
an encapsulation layer at least in contact with the isolation layer, wherein a top surface of the encapsulation layer, a top surface of the one or more memory layers, and a top surface of the isolation layer are substantially coplanar;
a top metallization layer arranged on top of the memory stack and the encapsulation layer, wherein
the top metallization layer comprises:
a diffusion barrier deposited on top of the memory stack, the isolation layer and the encapsulation layer; and
a top electrode arranged on top of the diffusion barrier; and
the top electrode layer is in direct contact with a top surface of the diffusion barrier.
2. The memory cell of claim 1 , wherein the one or more memory layers comprise a high-k gate dielectric that is capable of acting as an RRAM element.
3. The memory cell of claim 2 , wherein the high-k gate dielectric is HfO 2 .
4. The memory cell of claim 1 , wherein the isolation layer is SiN.
5. The memory cell of claim 1 , wherein the top electrode is a line.
6. The memory cell of claim 1 , wherein the diffusion barrier is TiN.
7. The memory cell of claim 1 , wherein the one or more memory layers comprise an MTJ stack.
8. A memory cell comprising:
a bottom electrode that comprises a via upon a bottom line, the bottom line arranged along a first direction;
a memory stack upon the via, wherein the memory stack comprises:
one or more memory layers that are configured to store data, the one or more memory layers in direct contact with a top surface of the bottom line and in direct contact with a lateral side(s) of the via; and
an isolation layer directly upon the one or more memory layers;
an encapsulation layer directly upon the isolation layer, wherein a top surface of the encapsulation layer, a top surface of the one or more memory layers, and a top surface of the isolation layer are substantially coplanar; and
a top electrode arranged in a second direction that is substantially perpendicular to the first direction, wherein the top electrode comprises:
a diffusion barrier deposited on top of the memory stack, the isolation layer and the encapsulation layer; and
a top electrode conductor arranged on top of the diffusion barrier; and
the top electrode conductor is in contact with at least the top surface of the diffusion barrier.
9. The memory cell of claim 8 , wherein the one or more memory layers comprise a high-k gate dielectric that is capable of acting as an RRAM element.
10. The memory cell of claim 9 , wherein the high-k gate dielectric is HfO 2 .
11. The memory cell of claim 8 , wherein the isolation layer is SiN.
12. The memory cell of claim 8 , wherein the top electrode is a line.
13. The memory cell of claim 8 , wherein the diffusion barrier is TiN.
14. The memory cell of claim 8 , wherein the one or more memory layers comprise an MTJ stack.
15. A memory cell comprising:
a bottom line associated with a via thereupon, the bottom line arranged along a first direction;
a memory stack upon the via, wherein the memory stack comprises:
one or more memory layers that are configured to store data, the one or more memory layers in direct contact with a top surface of the bottom line and in direct contact with a lateral side(s) of the via; and
an isolation layer directly upon the one or more memory layers;
an encapsulation layer directly upon the isolation layer, wherein a top surface of the encapsulation layer, a top surface of the one or more memory layers, and a top surface of the isolation layer are substantially coplanar; and
a top line arranged in a second direction that is substantially perpendicular to the first direction, wherein the top line comprises:
a diffusion barrier deposited on top of the memory stack, the isolation layer and the encapsulation layer; and
a top electrode conductor arranged on top of the diffusion barrier; and
the top electrode conductor is in contact with the top surface of the diffusion barrier.
16. The memory cell of claim 15 , wherein the one or more memory layers comprise a high-k gate dielectric that is capable of acting as an RRAM element.
17. The memory cell of claim 16 , wherein the high-k gate dielectric is HfO 2 .