Manufacturing method of three-dimensional semiconductor device
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a sacrificial source layer on a source layer;
forming a first select gate layer on the sacrificial source layer;
alternately stacking a sacrificial layer and an interlayer insulating layer on the first select gate layer;
forming a hole in which an insulating structure covers a surface within the hole, wherein the hole penetrates the interlayer insulating layer, the sacrificial layer, the first select gate layer, and the sacrificial source layer, and extends into the source layer;
sequentially stacking a data storage layer and a tunnel insulating layer, on the insulating structure;
forming a channel structure on the tunnel insulating layer by filling the hole with the channel structure;
removing the sacrificial source layer; and
selectively oxidizing the first select gate layer from a bottom surface of the first select gate layer to form an extended insulating portion connected to the insulating structure.
2. The method of claim 1 , further comprising:
before forming the sacrificial source layer, forming a first protective layer on the source layer;
before forming the first select gate layer, forming a second protective layer on the sacrificial source layer; and
after removing the sacrificial source layer, removing the second protective layer;
wherein the first protective layer is oxidized while the first select gate layer is selectively oxidized.
3. The method of claim 1 , further comprising:
before selectively oxidizing the first select gate layer, etching the insulating structure to expose the data storage layer between the source layer and the first select gate layer;
after selectively oxidizing the first select gate layer, sequentially etching the data storage layer and the tunnel insulating layer to expose a sidewall of the channel structure between the source layer and the first select gate layer; and
forming a source-channel contact layer on an exposed sidewall of the channel structure and the insulating structure.
4. The method of claim 3 , wherein the sequentially etching of the data storage layer and the tunnel insulating layer is performed so that a portion of the channel structure that faces a sidewall of the first select gate layer is exposed.
5. The method of claim 1 , wherein the selectively oxidizing of the first select gate layer is controlled such that an oxide thickness of the first select gate layer is greater than that of the tunnel insulating layer.
6. The method of claim 1 , further comprising replacing the sacrificial layer with a conductive material.
7. The method of claim 1 , wherein the forming of the hole, in which the insulating structure covers the surface within the hole, includes:
etching the interlayer insulating layer, the sacrificial layer, the first select gate layer, and the sacrificial source layer to expose sidewalls of the interlayer insulating layer, the sacrificial layer, the first select gate layer, and the sacrificial source layer;
forming a liner layer extending over the exposed sidewalls of the interlayer insulating layer, the sacrificial layer, the first select gate layer, and the sacrificial source layer; and
forming the insulating structure using an oxidation process with a higher oxidation rate with respect to the first select gate layer than the liner layer.
8. The method of claim 7 , wherein a portion of the first select gate layer overlapping with the sacrificial layer is oxidized through the oxidation process.