Three-dimensional semiconductor device
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.
1 . A semiconductor memory device comprising:
a first select gate layer;
a stack including interlayer insulating layers and word lines alternately disposed in a first direction over the first select gate layer; and
an insulating pattern extending in the first direction to cover a sidewall of the first select gate layer and a sidewall of the stack,
wherein the insulating pattern includes a first portion covering the sidewall of the first select gate layer and a second portion extending from the first portion to cover a sidewall of each of the word lines, and
wherein the first portion is thicker than the second portion.
2 . The semiconductor device of claim 1 ,
wherein the first portion of the insulating pattern overlaps a bottom of each of the word lines.
3 . The semiconductor device of claim 1 , further comprising:
a semiconductor layer including a portion overlapping a sidewall of the first select gate layer,
wherein the semiconductor layer is spaced apart from the first select gate layer by the insulating pattern.
4 . The semiconductor device of claim 3 , further comprising:
a source layer connected to the semiconductor layer and extending to overlap a bottom of the first select gate layer,
wherein the first select gate layer is disposed between the source layer and the stack.
5 . The semiconductor device of claim 4 ,
wherein the source layer includes a doped silicon.
6 . The semiconductor device of claim 1 , further comprising:
a source layer overlapping a bottom of the first select gate layer and spaced apart from the first select gate layer;
a bit line over the stack;
a channel structure extending from inside a groove of the source layer toward the bit line; and
a data storage layer extending along a sidewall of the channel structure.
7 . The semiconductor device of claim 6 , further comprising:
a doped semiconductor layer surrounding a portion of the channel structure between the first select gate layer and the source line.
8 . The semiconductor device of claim 6 ,
wherein each of the word lines and the first select gate layer surrounds a channel structure, and
wherein the data storage layer is interposed between the channel structure and each of the word lines and the first select gate layer.
9 . The semiconductor device of claim 1 , further comprising:
a second select gate layer disposed between the first select gate layer and the stack and connected to the first select gate layer.